View BCM20733_8883386.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

cyw20733 single-chip bluetooth transceiver wireless input devices cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document no. 002-14859 rev. *r revised october 21, 2016 the cypress cyw20733 is a bluetooth 3.0 + edr compliant, stand-alone baseband proc essor with an integrated 2.4 ghz trans- ceiver. the device is ideal for applicatio ns in wireless input devices including ga me controllers, keyboards, and joysticks. bu ilt-in firmware adheres to the bluetooth human interface device (hid) profile and bluetooth device id profile specifications. the cyw20733 radio has been designed to provide low power, low cost, and robust communications for applications operating in the globally available 2.4 ghz unlicensed ism b and. it is fully compliant with the bluetoot h radio specification 3.0 + edr. the sin gle- chip bluetooth transceiver is a monolithic component implemented in a standard digita l cmos process and requires minimal exter- nal components to make a fully compliant bluetooth device. the cyw20733 is available in three package options: a 81-pin, 8 mm 8 mm fbga, a 121-pin, 9 mm 9 mm fbga , and a 56-pin, 7 mm x 7 mm qfn. cypress part numbering scheme cypress is converting the acquired iot part nu mbers from broadcom to the cypress part numbering scheme. due to this conversion, there is no change in form, fit, or functi on as a result of offering the device with cypress part number marking. the table pro vides cypress ordering part number that matches an existing iot part number. table 1. mapping table for part number between broadcom and cypress features integrated ldo to reduce bom cost bluetooth specification 3.0 + edr compatible bluetooth hid profile version 1.1 compliant bluetooth device id profile version 1.3 compliant supports afh excellent receiver sensitivity on-chip support for common keyboard and mouse inter- faces eliminates external processor infrared (ir) modulator ir learning integrated 200 mw filterless class-d audio amplifier triac control triggered broadcom fast connect one i/o capable of sinking 100 ma for high- current drive applications programmable key scan matrix interface, up to 8 20 key- scanning matrix three-axis quadrature signal decoder on-chip support for serial peripheral interface (master and slave modes) broadcom serial communications interface (compatible with philips? i2c slaves) two independent half-duplex pcm/i2s interfaces real-time clock supported with 32.768 khz oscillator programmable output power control meets class 2 or class 3 requirements on-chip pa with a maximum output power of +10dbm with- out external component integrated arm7tdmi-s?- based microprocessor core on-chip power on reset (por) on-chip software control power management unit three package types available: ? 81-pin fbga package (8 mm 8 mm) ? 121-pin fbga package (9 mm 9 mm) ? 56-pin qfn package (7 mm x 7 mm) rohs compliant applications game controllers wireless pointing device s: mice, trackballs wireless keyboards joysticks point-of-sale (pos) input devices remote controls home automation 3d glasses broadcom part number cypress part number BCM20733 cyw20733 BCM20733a3kfb1g cyw20733a3kfb1g BCM20733a3kfb2g cyw20733a3kfb2g BCM20733a3kml1g cyw20733a3kml1g
document no. 002-14859 rev. *r page 2 of 67 cyw20733 figure 1. functional block diagram keyboard matrix scanner w/fifo 3-axis mouse signal controller processing unit (arm7) system bus bluetooth baseband core 2.4 ghz radio rf control and data t/r switch rf i/o gpio control/ status registers frequency synthesizer 57 gpio pins ref xtal ldo ctrl i/o ring bus i/o ring control registers peripheral interface block 1.2v vddc domain vddo domain wake 1.2v ldo 1.62v -3.6v 1.2v vddc volt. trans bsc/spi master interface (bsc is i2c- compat) sda/ mosi sck 6 quadrature inputs (3 pair) + hi -current driver controls 8 x 20 scan matrix 57 gpio 32 khz lpclk 28 adc inputs 24 mhz 24 mhz autocal miso 1.2v vddrf domain pwm wdt 128 khz lpo 4 32 khz lpclk 128 khz lpclk 32 khz xtal (op ? onal) power 1.2v por 1.2v test uart ir i/o ir mod. and learning spi m/s mia por ct gp adc 28 adc inputs vss, vddo, vddc periph uart tx rx rtsn ctsn muxed on gpio 384k rom 80k ram high sink io pmu digital audio block tx rx rtsn ctsn class-d driver speaker 3v speaker out
document no. 002-14859 rev. *r page 3 of 67 cyw20733 contents 1.functional descript ion ............ ................ ........... 4 1.1 integrated radio transceiv er .............................. 4 1.1.1 transmitter path ...................................... 4 1.1.2 receiver path .......................................... 4 1.1.3 local oscillator ........................................ 4 1.1.4 calibration ............................................... 4 1.1.5 internal ldo regulator ............................ 4 1.2 microprocessor unit ........ .................................... 5 1.2.1 eeprom interface .... ........... ........... ........ 5 1.2.2 serial flash interface ............................... 5 1.2.3 internal reset .......................................... 5 1.2.4 external reset ......................................... 6 1.3 bluetooth baseband core .. .............. ........... ........ 6 1.3.1 frequency hopping g enerator ..... ........... 6 1.3.2 e0 encryption .......................................... 6 1.3.3 link control layer ................................... 6 1.3.4 adaptive frequency hopping ..... ............. 6 1.3.5 bluetooth version 3.0 features ............... 6 1.3.6 test mode support . .............. ........... ........ 7 1.4 peripheral transport unit (ptu) ......................... 7 1.4.1 broadcom serial cont rol interface .......... 7 1.4.2 uart interface ........................................ 8 1.5 pcm interface ..................................................... 9 1.5.1 system diagram ...................................... 9 1.5.2 slot mapping .......................................... 10 1.5.3 frame synchronization .......................... 10 1.5.4 data formatting ..................................... 10 1.6 i 2 s interface ...................................................... 10 1.7 clock frequencies ............................................ 10 1.7.1 crystal oscillator ................................... 10 1.8 gpio port .......................................................... 12 1.9 keyboard scanner ............................................ 12 1.9.1 theory of operation ............................... 13 1.10 mouse quadrature signal decoder ................... 13 1.10.1 theory of operation ............................... 13 1.11 adc port ........................................................... 13 1.12 pwm ................................................................. 14 1.13 serial peripheral interf ace ................................. 15 1.14 infrared modulator ..............................................18 1.15 infrared learning ................................................19 1.16 shutter control for 3d glasses ..........................19 1.17 triac control .......................................................20 1.18 cypress proprietary control signalling and triggered broadcom fa st connect .............20 1.19 integrated filterless class-d audio amplifier .....20 1.20 high-current i/o .................................................21 1.21 power management unit ....................................22 1.21.1 rf power management ..........................22 1.21.2 host controller power management ......22 1.21.3 bbc power management .......................22 2.pin assignments............................................... 23 2.1 ball maps ...........................................................29 2.1.1 81-pin fbga ball map ...........................29 2.1.2 121-pin fbga ball map ........... ..............31 2.1.3 56-pin qfn diagram ..............................32 3.specifications.................................................... 33 3.1 electrical characteristics ....................................33 3.2 rf specifications ...............................................37 3.3 timing and ac characterist ics ............. ..............39 3.3.1 uart timing ..........................................39 3.3.2 spi timing ..............................................40 3.3.3 bsc interface timing .............................41 3.3.4 pcm interface timing .............................43 3.3.5 i 2 s timing ...............................................48 4.mechanical information. ................................... 53 4.0.1 tape reel and packaging specifications .........................................56 5.ordering information ........................................ 62 6.iot resources ................................................... 62 a.acronyms and abbreviations.......................... 62 document history........................................................... 64 sales, solutions, and legal information ...................... 67
document no. 002-14859 rev. *r page 4 of 67 cyw20733 1. functional description 1.1 integrated radio transceiver the cyw20733 has an integrated radio transce iver that has been optimized for use in 2.4 ghz bluetoot h wireless systems. it has been designed to provide low power, low cost, robust communicatio ns for applications operating in the globally available 2.4 gh z unlicensed ism band. it is fully compliant wit h bluetooth radio specification 3.0 + edr and meets or exceeds the requirements t o provide the highest communication link quality of service. 1.1.1 transmitter path the cyw20733 features a fully integrated zero if transmitter. the baseband transmit data is gfsk modulated in the modem block and upconverted to the 2.4 ghz ism band. the tr ansmit path consists of signal filtering, i/q upconversion, output power amplification, and rf filtering. it also incorporates the ? /4-dqpsk and 8-dpsk modulation schemes, which support the 2 mbps and 3 mbps enhanced data rates, respectively. digital modulator the digital modulator performs the data modu lation and filtering required for the gfsk, ? /4-dqpsk, and 8-dpsk signals. the fully digital modulator minimizes any frequen cy drift or anomalies in the modulation characteristics of the transmitted signal and is much more stab le than direct vco modulation schemes. power amplifier the integrated power amplifier (pa) for the cyw20733 can transmit at a maximum power of +4 dbm for class 2 operation. the transm it power levels are for basic rate and edr. due to the linear nature of the pa, combined with some integrated filtering, no extern al filters are required for meeting bluetooth and regulat ory harmonic and spurious requirements. the cyw20733 internal pa can deliver a maximum output power of +10 dbm for basic rate and +8 dbm for edr with a flexible supply range of 2.5v to 3.0v. 1.1.2 receiver path the receiver path uses a low-if scheme to downconvert the rece ived signal for demodulation in the digital demodulator and bit synchronizer. the receiver path provides a high degree of linear ity, an extended dynamic range, and high-order on-chip channel filtering to ensure reliable operation in the noisy 2.4 ghz ism band. the front-end topology wi th built-in out-of-band attenuat ion enables the cyw20733 to be used in most applications without off-chip filtering. digital demodulator and bit synchronizer the digital demodulator and bit synchronizer take the low-if received signal and perform an optimal frequency tracking and bit synchronization algorithm. receiver signal strength indicator the radio portion of the cyw20733 provides a receiver signal st rength indicator (rssi) to the baseband. this enables the contro ller to take part in a bluetooth power-controlled link by providing a me tric of its own receiver signal strength to determine whethe r the transmitter should increase or decrease its output power. 1.1.3 local oscillator the local oscillator (lo) provides fast frequency hopping (1600 hops/second) across the 79 maximum available channels. the lo subblock employs an architecture for high immunity to lo pulling during pa operation. the cyw20733 uses an internal rf and if loop filter. 1.1.4 calibration the cyw20733 radio transceiver features an autom ated calibration scheme that is self-con tained in the radio. no user interactio n is required during normal operation or during manufacturing to provide the optimal perfor mance. calibration will optimize the gain and phase performance of all the major blocks within the radio to wi thin 2% of optimal conditions. calibrated blocks include filter s, the matching networks between key components , and key gain blocks. the calibration process corrects fo r both process and temperatur e variations. it occurs transparently during normal operation and t he setting time of the hops an d will calibrate for temperature variations as the device cools and heats during normal operation in its environment. 1.1.5 internal ldo regulator to reduce the external bom, t he cyw20733 has an integrated 1.2v ldo regulator to provide power to the digital and rf circuits a nd system components. the 1.2v ldo regulator operates from a 1.62v to 3.63v input supply with a 60 ma maximum load current. in noisy environments, a ferrite bead may be needed between the di gital and rf supply pins to isolate noise coupling and suppre ss noise into the rf circuits. note: always place the decoupling capacitors near the pins as close together as possible.
document no. 002-14859 rev. *r page 5 of 67 cyw20733 1.2 microprocessor unit the cyw20733 microprocessor unit (pu) runs software from the link control (lc) layer up to the human interface device (hid). t he microprocessor is based on an arm7? 32-bit risc processor with embedded ice-rt debug and jtag interface units. the pu has 320 kb of rom for program storage and boot-up, 80 kb of ram for scratch-pad data, and patch ram code. the internal boot rom allows for flexibility during power-on reset to enable the same device to be used in various configuratio ns, including uart, and with an external serial eeprom or with an external flash memory. at power- up, the lower layer protocol stac k is executed from the internal rom memory. external patches may be applied to the rom- based firmware to provide flexibility for b ug fixes and feature additions. the devic e can also support the integrati on of user applications. 1.2.1 eeprom interface the cyw20733 provides the bsc (broadcom serial control) master interface; the bsc is programmed by the cpu to generate four different types of bsc transfers on the bus : read-only, write-only, combined read/writ e, and combined write/ read. bsc supports both low-speed and fast mode devices. the bsc is compatible with a philips? i 2 c slave device, except that master arbitration (multiple i 2 c masters contending for the bus) is not su pported. native support for microchip? 24l c128, microchip 24aa128, and stmicroelec- tronics? m24128-br is included. the eeprom can contain customer applicati on configuration in formation, including: application code, conf iguration dat a, patches , pairing information, bd_addr, baud rate, sdp service record, and file system information used for code. 1.2.2 serial flash interface the cyw20733 includes an spi master controller that can be used to access serial flash memory. the spi master contains an ahb slave interface, transmit and receive fi fos, and the spi core phy logic. devices natively supported include the following: atmel? at25bcm512b mxic mx25v512zui-20g 1.2.3 internal reset the cyw20733 has an integrated power-on reset circuit t hat resets all circuits to a known power-on state. figure 1. internal reset timing vddo vddo ? por vddc vddo ? por ? threshold vddo ? por ? delay ~ ? 2 ? ms vddc ? por vddc ? por ? threshold vddc ? por ? delay ~ ? 2 ? ms baseband ? reset crystal ? warm \ up ? delay: ? ~ ? 5 ? ms crystal ? enable start ? reading ? eeprom ? and ? firmware ? boot.
document no. 002-14859 rev. *r page 6 of 67 cyw20733 1.2.4 external reset an external active-low reset signal, reset_n, can be used to put the cyw20733 in the reset state. the reset_n pin has an intern al pull-up resistor and, in most applications, it does not require that anything be co nnected to it. reset_n should only be releas ed after the vddo supply voltage level has been stabilized. figure 2. external reset timing 1.3 bluetooth baseband core the bluetooth baseband core (bbc) implements all of the time-c ritical functions required for hi gh-performance bluetooth operati on. the bbc manages the buffering, segmentation, and routing of dat a for all connections. it also buffers data that passes through it, handles data flow control, schedul es acl tx/rx transactions, monitors bluetooth sl ot usage, optimally segments and packages dat a into baseband packets, manages connecti on status indicators, and composes and decodes hci packets. in addition to these functions, it independently handles hci event types and hci command types. the following transmit and receive functions are also implemented in the bbc hardware to increase reliability and security of t he tx/ rx data before sending over the air: receive functions: symbol timing recovery, data deframing, forw ard error correction (fec), head er error control (hec), cyclic redundancy check (crc), data decryption, and data de-whitening. transmit functions: data framing, fec g eneration, hec generation, crc generation, link key generation, data encryption, and data whitening. 1.3.1 frequency hopping generator the frequency hopping sequence generator selects the correct ho pping channel number depending on the link controller state, bluetooth clock, and the device address. 1.3.2 e0 encryption the encryption key and the encryption engine are implemented using dedicated hardware to reduce software complexity and provide minimal intervention. 1.3.3 link control layer the link control layer is part of the blue tooth link control functions t hat are implemented in dedicated logic in the link cont rol unit (lcu). this layer consists of the command controller, which ta kes commands from the software, and other controllers that are activated or configured by the command co ntroller to perform the link control tasks. each task perfo rms in a different state in the bluetooth link controller. standby and connect ion are the two major states. in addition , there are five substates: page, page scan, inquiry, inquiry scan, and sniff. 1.3.4 adaptive frequency hopping the cyw20733 gathers link quality statistics on a channel-by-channe l basis to facilitate channel assessment and channel map selection. the link quality is determined using both rf and base band signal processing to provide a more accurate frequency-hop map. 1.3.5 bluetooth version 3.0 features the cyw20733 is fully compliant with the bluetoot h 3.0 standard, including the following options: reset_n pulse ? width >20 ? s crystal ? enable baseband ? reset start ? reading ? eeprom ? and ? firmware ? boot. crystal ? warm \ up ? delay: ? ~ ? 5 ? ms
document no. 002-14859 rev. *r page 7 of 67 cyw20733 enhanced power control hci read, encryption key size command the cyw20733 supports all of the new bluetooth version 2.1 features: extended inquiry response sniff subrating encryption pause and resume secure simple pairing link supervision timeout changed event erroneous data reporting non-automatically flushable packet boundary flag security mode 4 1.3.6 test mode support the cyw20733 fully supports bluetooth test mode, as described in part 1 of the bluetooth system version 2.1 specification. this includes the transmitter tests, normal and delayed loopback tests, and reduced hopping sequence. in addition to the standard bluetooth test mode, the device s upports enhanced testin g features to simplify rf debugging and qua lifi- cation and type approval testing. these features include: fixed frequency carrier wave (unmodulated) transmission simplified type approval measurements (japan) aid in transmitter performance analysis fixed frequency constant receiver mode receiver output directed to i/o pin direct ber measurements usin g standard rf test equipment facilitated spurious emissi ons testing for receive mode fixed frequency constant transmission 8-bit fixed pattern or prbs-9 modulated signal measurements with standard rf test equipment connectionless transmitter test hopping or fixed frequency multiple packet types multiple data patterns connectionless receiver test 1.4 peripheral transport unit (ptu) 1.4.1 broadcom serial control interface the cyw20733 provides a 2-pin master bsc in terface that can be used to retrieve c onfiguration information from an external eeprom or to communicate with peripherals such as track-ball or touch-pad modules, and motion tracking ics used in mouse devices. the bsc interface is compatible with i 2 c slave devices. the bsc does not support multimaster capability or flexible wait- state insertion by either master or slave devices. listed below are the transfer clock rates supported by the bsc: 100 khz 400 khz 800 khz (not a standard i 2 c-compatible speed.)
document no. 002-14859 rev. *r page 8 of 67 cyw20733 4 mhz maximum (compatibility with high-speed i 2 c-compatible devices is not guaranteed.) the following transfer types are supported by the bsc: read (up to 127 bytes can be read) write (up to 127 bytes can be written) read-then-write (up to 127 bytes can be read , and up to 127 bytes can be written.) write-then-read (up to 127 bytes can be wr itten, and up to 127 bytes can be read.) hardware controls the transfers, requiring minimal firmware setup and supervision. the clock pin (scl) and data pin (sda) are both open-drain i/o pins. pull -up resistors external to the cyw20733 are required on both scl and sda for proper operation. 1.4.2 uart interface the uart physical interface is a standard, 4-wire interface (rx, tx, rts, and cts) wit h adjustable baud rates from 9600 bps to 1 .5 mbps. during initial boot, uart speeds may be limited to 750 kbps. the baud rate may be selected via a vendor-specific uart hci command. the cyw20733 has a 1040-byte receive fifo and a 1 040-byte transmit fifo to support enhanced data rates. the interface supports the bluetooth 3.0 uart hci (h4) specif ication. the default baud rate for h4 is 115.2 kbaud. the uart clock is 24 mhz. the baud rate of the cyw20733 uart is controlled by two values. the first is a uart clock divisor (als o called the dlbr register) that divides the uart clock by an in teger multiple of 16. the second is a baud rate adjustment (also called the dhbr register) that is used to specify a number of uart cloc k cycles to stuff in the first or second half of each bit time. up to eight uart cycles can be inserted into the fi rst half of each bit time, and up to ei ght uart clock cycles can be inserted into the end of each bit time. when setting the baud rate manually, the uart clock divisor is an 8-bit value that is stored as 256 minus the chosen divisor. f or example, a divisor of 13 is stored as 256 ? 13 = 243 = 0xf3. the baud rate adjustment is also an 8-bit va lue, of which the four msbs are the number of additional clock cycles to insert in the first half of each bit time, and the four lsbs are the number of clock cycles to insert in the second half of eac h bit time. if eithe r of these two values is over eight, it is rounded to eight. to compute the baud rate, the calculation is expressed as: 24 mhz ((16 uart clock divisor) + total inserted 24-mhz clock cycles) ta b l e 2 contains example values to generate common baud rates. normally, the uart baud rate is set by a configuration record downloaded after reset. support for changing the baud rate during normal hci uart operation is included through a vendor-specific co mmand that allows the host to adjust the contents of the baud rate registers. the cyw20733 uart operates correctly with t he host uart as long as the combined baud rate error of the two devices is within 5 %. peripheral uart interface the cyw20733 has a second uart that may be used to interface to other peripherals. this peripheral uart is accessed through the optional i/o ports, which can be conf igured individually and separately for each functional pin as shown in table 3 . table 2. common baud rate examples desired baud rate (bps) uart clock divi- sor baud rate adjustment actual baud rate (bps) error (%) high nibble low nibble 1500000 0xff 0x00 0x00 1500000 0.00 921600 0xff 0x05 0x05 923077 0.16 460800 0xfd 0x02 0x02 461538 0.16 230400 0xfa 0x04 0x04 230769 0.16 115200 0xf3 0x00 0x00 115385 0.16 57600 0xe6 0x00 0x00 57692 0.16 38400 0xd9 0x01 0x00 38400 0.00 28800 0xcc 0x00 0x00 28846 0.16 19200 0xb2 0x01 0x01 19200 0.00 14400 0x98 0x00 0x00 14423 0.16 9600 0x64 0x02 0x02 9600 0.00
document no. 002-14859 rev. *r page 9 of 67 cyw20733 1.5 pcm interface the cyw20733 pcm interface can connect to linear pcm codec devic es in master or slave mode . in master mode, the device generates the pcm_bclk and pcm_sync signals. in slave mode, these signals are provided by another master on the pcm interface as inputs to the device. the channels can be configured to either transmit or receive, but they must be assigned to different time slots. the two half-d uplex channels cannot be combined to form a single full-duplex channel. 1.5.1 system diagram figure 3 shows options for connecting the device to a pcm codec device as a master or a slave. figure 3. pcm interface with linear pcm codec table 3. cyw20733 peripheral uart pin name puart_tx puart_rx puart_cts_n puart_rts_n configured pin name p0 p2 p3 p1 p5 p4 p7 p6 p24 p25 p35 p30 p31 p33 ? ? p32 p34 ? ? pcm ? interface ? slave ? mode pcm ? codec (master) cyw20733 (slave) pcm_in pcm_bclk pcm_sync pcm_out pcm ? interface ? master ? mode pcm ? codec (slave) cyw20733 (master) pcm_in pcm_bclk pcm_sync pcm_out pcm ? interface ? hybrid ? mode pcm ? codec (hybrid) cyw20733 (hybrid) pcm_in pcm_bclk pcm_sync pcm_out
document no. 002-14859 rev. *r page 10 of 67 cyw20733 1.5.2 slot mapping the pcm data output driver tri-states its output on unused slots to allow other devices to share the same pcm interface signals . the data output driver tristates its outp ut after the falling edge of the pcm clock during the last bit of the slot. 1.5.3 frame synchronization the device supports both short and long frame synchronization types in both master and slave co nfigurations. in short frame syn chro- nization mode, the frame synchronization signal is an active-high pulse at the 8 khz audio frame rate (which is a single bit per iod in width) and synchronized to the rising edge of the bit clock. th e pcm slave expects pcm_sync to be high on the falling edge of t he bit clock and the first bit of the first slot to start at the next rising edge of the clock. in the long frame synchronization mode, the frame synchronization signal is an active-high pulse at the 8 khz audi o frame rate. however, the duration is 3-bit periods, and the pu lse starts coincident with the first bit of the first slot. 1.5.4 data formatting the device can be configured to generate and accept several differ ent data formats. the device uses 13 of the 16 bits in each p cm frame. the location and order of these 13 bi ts is configurable to support various data formats on the pcm interface. the remain ing three bits are ignored on the input and may be filled with zeros, ones, a sign bit, or a programmed value on the output. the de fault format is 13-bit two?s complement data, left justified, and clocked most significant bit first. 1.6 i 2 s interface the i 2 s interface supports up to two half-duplex c hannels. the channels can be configured to ei ther transmit or receive, but they mus t be assigned to different time slots (left or right). the two ha lf-duplex channels cannot be combined to form a single full-dupl ex channel. the i 2 s interface is capable of operating in eith er slave or master mode. the device sup ports a 16-bit data width with 8-khz and 16- khz frame rates. 1.7 clock frequencies the cyw20733 is set with a crystal frequency of 24 mhz. 1.7.1 crystal oscillator the crystal oscillator requires a crystal with an accuracy of 20 ppm as defined by the bluetooth specification. two external l oad capacitors in the 5 pf to 30 pf range are required to work wit h the crystal oscillator. the sele ction of the load capacitors is crystal dependent. ta b l e 5 shows the recommended crystal specification. table 4. pcm interface time-slotting scheme audio sample rate time-slotting scheme 8 khz the number of slots depends on the selected interface rate, as follows: interface rate slot 1281 2562 5124 10248 204816 16 khz the number of slots depends on the selected interface rate, as follows: interface rate slot 2561 5122 10244 20488
document no. 002-14859 rev. *r page 11 of 67 cyw20733 figure 4. recommended oscillator configuration?12 pf load crystal hid peripheral block the peripheral blocks of the cyw 20733 all run from a single 128-khz low-power rc oscillator. the oscillat or can be turned on at the request of any of the peripherals. if a peripheral is not enabled, it shall not assert its clock request line. the keyboard scanner is a special case in that it may drop its clock request line even when enabled and then reassert the clock request line if a key-press is detected. real-time clock and 32 khz crystal oscillator the cyw20733 has a 48-bit counter that can be configured to be clocked directly from a 32.768 khz or 32.000 khz crystal oscillato r. the real-time clock counter value is accessible via firmware. figure 5 shows the 32 khz crystal (xtal) oscillator with external components, and table 6 lists the oscillator?s characteristics. it is a standard pierce oscillator using a comparator with hysteresis on the output to crea te a single-ended digital output. the hyster esis was added to eliminate any chatter when the input is around the thre shold of the comparator and is ~100 mv. this circuit can be ope rated with a 32 khz or 32.768 khz crystal oscillator or be driven with a clock input at a similar fr equency. the default component va lues are: r1 = 10 m ? , c1 = c2 = ~10 pf. the values of c1 and c2 are used to fine-tune the oscillator. table 5. reference crystal electrical specifications parameter conditions min typ max unit input signal amplitude ? 400 ? 2000 mvp-p nominal frequency ? ? 24.000 ? mhz oscillation mode ? fundamental ? frequency tolerance @25c ? 10 ? ppm tolerance stability over temp @0c to +70c ? 10 ? ppm equivalent series resistance ? ? ? 50 ? load capacitance ? ? 12 ? pf operating temperature range ? 0 ? +70 c storage temperature range ? ?40 ? +125 c drive level ? ? ? 200 ? w aging ? ? ? 10 ppm/year shunt capacitance ? ??2pf
document no. 002-14859 rev. *r page 12 of 67 cyw20733 figure 5. 32-khz oscillator block diagram 1.8 gpio port the cyw20733 has 40 general-purpose i/os (g pios) in the 81-pin package and 58 gpios in the 121-pin package. all gpios support programmable pull-ups and are capable of driving up to 8 ma at 3.3v or 4 ma at 1.8v, except p26, p27, p28, and p29, which are capable of driving up to 16 ma at 3.3v or 8 ma at 1.8v. gpio p57 is capable of sinking 100 ma for vddio = 3.0v and 60 ma for vddio = 1.62v. port 0?port 1, port 8?port 18, po rt 20?port 23, and port 28?port 38 all of these pins can be programmed as adc inputs. port 26?port 29 p[26:29] consist of four pins. all pins are capable of sinking up to 16 ma for leds. these pins also have the pwm function, whic h can be used for led dimming. 1.9 keyboard scanner the keyboard scanner is designed to autonomously sample keys and store them into buffer registers without the need for the host microcontroller to intervene. the scanner has the following features: ability to turn off its cl ock if no keys are pressed. sequential scanning of up to 160 keys in an 8 20 matrix. programmable number of columns from 1 to 20. programmable number of rows from 1 to 8. 16-byte key-code buffer (can be augmented by firmware). 128 khz clock?allows scanning of full 160-key matrix in about 1.2 ms. n-key rollover with selective 2-key lockout if ghost is detected. keys are buffered until host microcontroller has a ch ance to read it, or until overflow occurs. table 6. xtal oscillator characteristics parameter symbol conditions minimum typical maximum unit output frequency f oscout ? ? 32.768 ? khz frequency tolerance ? crystal dependent ? 100 ? ppm start-up time t startup ? ? ? 500 ms xtal drive level p drv for crystal selection 0.5 ? ? ? w xtal series resistance r series for crystal selection ??70k ? xtal shunt capacitance c shunt for crystal selection ??1.3pf c2 c1 r1 32.768 ? khz xtal
document no. 002-14859 rev. *r page 13 of 67 cyw20733 hardware debouncing and noise/glitch filtering. low-power consumption. single-digit a-level sleep current. 1.9.1 theory of operation the key scan block is controlled by a st ate machine with the following states: idle the state machine begins in the idle state. in this state, all column outputs are driven high. if any key is pressed, a transit ion occurs on one of the row inputs. this transition causes the 128 khz cl ock to be enabled (if it is not already enabled by another perip heral) and the state machine to enter the scan state. also in this stat e, an 8-bit row-hit register and an 8-bit key-index counter is reset to 0. scan in the scan state, a row counter counts from 0 up to a programmabl e number of rows minus 1. after the last row is reached, the row counter is reset and the column counter is incremented. this cycle repeats until the row and co lumn counters are both at their respective terminal count values. at that point, the state machine moves into the scan-end state. as the keys are being scanned, the key-index counter is incremented. this counter is the value compared to the modifier key cod es stored, or in the key-code buffer if the key is not a modifier key. it can be used by the microprocessor as an index into a loo kup table of usage codes. also, as the n th row is scanned, the row-hit register is ored with the current 8-bit row input valu es if the current column contains two or more row hits. during the scan of any column, if a key is det ected at the current row, and the row-hit register indicates th at a hit was detected in that same row on a previous column, then a ghos t condition may have occurred, and a bit in the status register is set to indicate this. scan end this state determines whether any keys were detected while in the scan state. if yes, the state machine returns to the scan sta te. if no, the state machine returns to the idle state, an d the 128 khz clock request signal is made inactive. the microcontroller can poll the key status register. 1.10 mouse quadrature signal decoder the mouse signal decoder is designed to autonomously sample two quadr ature signals commonly generated by an optomechanical mouse. the decoder has the following features: three pairs of inputs for x, y, and z (typical scr oll wheel) axis signals. each axis has two options: ? for the x axis, choose p2 or p32 as x0 and p3 or p33 as x1. ? for the y axis, choose p4 or p34 as y0 and p5 or p35 as y1. ? for the z axis, choose p6 or p36 as z0 and p7 or p37 as z1. control of up to four external high-curre nt gpios to power external optoelectronics: ? turn-on and turn-off time can be staggered for each hc-gpio to avoid simultaneous switching of hi gh currents and having multipl e high-current devices on at the same time. ? sample time can be staggered for each axis. ? sense of the control signal can be active high or active low. ? control signal can be tristated for off condition or driven high or low, as appropriate. 1.10.1 theory of operation the mouse decoder block has four 10-bit pwms for controlling ex ternal quadrature devices and sampling the quadrature inputs at its core. the gpio signals may be used to control such items as leds, ex ternal ics that may emulate quadr ature signals, photodiodes, and photodetectors. 1.11 adc port the cyw20733 contains a 16-bit adc. additionally: there are 28 analog input channels. all channels are multiplexed on various gpios. there is a built-in reference wit h bandgap-based reference modes. the maximum conversion rate is 187 khz. there is a rail-to-rail input swing.
document no. 002-14859 rev. *r page 14 of 67 cyw20733 the adc consists of an analog adc core t hat performs the actual analog -to-digital conversion and digi tal hardware that processe s the output of the adc core into valid adc output samples. directed by t he firmware, the digital hardware also controls the inpu t multiplexers that select the adc input signal (v inp ) and the adc reference signals (v ref ). 1.12 pwm the cyw20733 has four internal pwms. the pwm module consists of the following: pwm1?4 each of the four pwm channels, pwm1?4, contains the following registers: ? 10-bit initial value register (read/write) ? 10-bit toggle register (read/write) ? 10-bit pwm counter value register (read) pwm configuration register shared among pwm1?4 (read/write). this 12-bit register is used: ? to configure each pwm channel ? to select the clock of each pwm channel ? to change the phase of each pwm channel figure 6 on page 15 shows the structure of one pwm. table 7. sampling rate and effective number of bits mode effective number of bits (enob) sampling rate (khz) latency a ( s) a. settling time of the adc and filter after switching channels. minimum typical 0 10.4 13.0 5.859 171 1 10.2 12.6 11.7 85 2 9.7 12.0 46.875 21 3 9.3 11.5 93.75 11 4 7.9 10.0 187 5
document no. 002-14859 rev. *r page 15 of 67 cyw20733 figure 6. pwm block diagram 1.13 serial pe ripheral interface the cyw20733 has two independent spi interfac es. one is a master-only interface (spi_1 ) and the other (spi_2) can be either a master or a slave. each interface has a 64-byte transmit buffer and a 64-byte receive buffer. to support more flexibility for u ser applications, the cyw20733 has optional i/o ports that can be conf igured individually and separately for each functional pin, a s shown in table 8 . the cyw20733 acts as an spi master device that supports 1. 8v or 3.3v spi slaves. the cyw20733 can also act as an spi slave device that supports a 1.8v or 3.3v spi master. note: spi voltage depends on vddo/vddm; th erefore, it defines the type of devices that can be supported. table 8. cyw20733 first spi set (master mode) pin name spi_clk spi_mosi spi_miso spi_cs a a. any gpio can be used as spi_cs when spi is in master mode. configured pin name scl sda p24 ? ??p26? ??p32 b b. default for serial flash. p33 b ??p39? pwm_cfg_adr ? register pwm#_init_val_adr ? register pwm#_togg_val_adr ? register pwm#_cntr_adr enable cntr ? value ? is ? arm ? readable clk_sel o_flip 10'h000 10'h3ff 10 10 10 example: ? pwm ? cntr ? w/ ? pwm#_init_val ? = ? 0 ? (dashed ? line) pwm ? cntr ? w/ ? pwm#_init_val ? = ? x ? (solid ? line) ?????????????????? 10'hx pwm_out pwm_togg_val_adr pwm_out
document no. 002-14859 rev. *r page 16 of 67 cyw20733 table 9. cyw20733 second spi set (master mode) configuration spi_clk spi_mosi spi_miso spi_cs a a. any gpio can be used as spi_cs when spi is in master mode. 1p3 p0p1? 2p3 p0p5? 3p3 p4p1? 4p3 p4p5? 5 p3 p27 p1 ? 6 p3 p27 p5 ? 7 p3 p38 p1 ? 8 p3 p38 p5 ? 9p7 p0p1? 10 p7 p0 p5 ? 11 p7 p4 p1 ? 12 p7 p4 p5 ? 13 p7 p27 p1 ? 14 p7 p27 p5 ? 15 p7 p38 p1 ? 16 p7 p38 p5 ? 17 p24 p0 p25 ? 18 p24 p4 p25 ? 19 p24 p27 p25 ? 20 p24 p38 p25 ? 21 p36 p0 p25 ? 22 p36 p4 p25 ? 23 p36 p27 p25 ? 24 p36 p38 p25 ?
document no. 002-14859 rev. *r page 17 of 67 cyw20733 table 10. cyw20733 second spi set (slave mode) configuration spi_clk spi_mosi spi_miso spi_cs 1p3 p0p1p6 2p3 p0p1p2 3p3 p0p5p6 4p3 p0p5p2 5 p3 p0 p25 p6 6 p3 p0 p25 p2 7p3 p4p1p6 8p3 p4p1p2 9p3 p4p5p6 10 p3 p4 p5 p2 11 p3 p4 p25 p6 12 p3 p4 p25 p2 13 p7 p0 p1 p2 14 p7 p0 p1 p6 15 p7 p0 p5 p6 16 p7 p0 p5 p2 17 p7 p0 p25 p2 18 p7 p0 p25 p6 19 p7 p4 p1 p6 20 p7 p4 p1 p2 21 p7 p4 p5 p6 22 p7 p4 p5 p2 23 p7 p4 p25 p2 24 p7 p4 p25 p6 25 p24 p27 p1 p26 26 p24 p27 p1 p32 27 p24 p27 p1 p39 28 p24 p27 p5 p26 29 p24 p27 p5 p32 30 p24 p27 p5 p39 31 p24 p27 p25 p26 32 p24 p27 p25 p32 33 p24 p27 p25 p39 34 p24 p33 p1 p26 35 p24 p33 p1 p32 36 p24 p33 p1 p39 37 p24 p33 p5 p26 38 p24 p33 p5 p32 39 p24 p33 p5 p39 40 p24 p33 p25 p26 41 p24 p33 p25 p32 42 p24 p33 p25 p39 43 p24 p38 p1 p26 44 p24 p38 p1 p32 45 p24 p38 p1 p39
document no. 002-14859 rev. *r page 18 of 67 cyw20733 1.14 infrared modulator the cyw20733 includes hardware support for infrared tx. the ha rdware can transmit both modulated and unmodulated waveforms. for modulated waveforms, hardware inserts the desired carrier frequency into all ir transmissions. ir tx can be sourced from firmware-supplied descriptors, a programmable bit, or the peripheral uart transmitter. if descriptors are used, they include ir on/off state and the du ration between 1?32767 sec. the cyw20733 ir tx firmware driver inserts this information in a hardware fifo and makes sure that all descriptors are played out without an underrun glitch. see figure 7 . 46 p24 p38 p5 p26 47 p24 p38 p5 p32 48 p24 p38 p5 p39 49 p24 p38 p25 p26 50 p24 p38 p25 p32 51 p24 p38 p25 p39 52 p36 p27 p1 p26 53 p36 p27 p1 p32 54 p36 p27 p1 p39 55 p36 p27 p5 p26 56 p36 p27 p5 p32 57 p36 p27 p5 p39 58 p36 p27 p25 p26 59 p36 p27 p25 p32 60 p36 p27 p25 p39 61 p36 p33 p1 p26 62 p36 p33 p1 p32 63 p36 p33 p1 p39 64 p36 p33 p5 p26 65 p36 p33 p5 p32 66 p36 p33 p5 p39 67 p36 p33 p25 p26 68 p36 p33 p25 p32 69 p36 p33 p25 p39 70 p36 p38 p1 p26 71 p36 p38 p1 p32 72 p36 p38 p1 p39 73 p36 p38 p5 p26 74 p36 p38 p5 p32 75 p36 p38 p5 p39 76 p36 p38 p25 p26 77 p36 p38 p25 p32 78 p36 p38 p25 p39 table 10. cyw20733 second spi set (slave mode) (cont.) configuration spi_clk spi_mosi spi_miso spi_cs
document no. 002-14859 rev. *r page 19 of 67 cyw20733 figure 7. infrared tx 1.15 infrared learning the cyw20733 includes hardware support for infrared learning. th e hardware can detect both modulated and unmodulated signals. for modulated signals, the cyw20733 can detect carrier frequencies between 10?500 khz and the duration that the signal is present or absent. the cyw20733 firmw are driver supports further analysis and compression of a learne d signal. a learne d signal can then be played back throug h the cyw20733 ir tx subsystem. see figure 8 . figure 8. infrared rx 1.16 shutter control for 3d glasses the cyw20733, combined with t he cyw20702, provides full system support for 3d glasses on televisions. the cyw20702 gets frame synchronization signals from the tv, converts them into proprietary timing control messages, then passes the messages to the cyw20733. the cyw20733 uses these messages to synchronize the s hutter control for the 3d glasses with the television frames. cyw20733 r1 vcc q1 r2 infrared \ ld d1 ir ? tx u1 cyw20733 vcc d2 photodiode ir ? rx u3
document no. 002-14859 rev. *r page 20 of 67 cyw20733 the cyw20733 can provide up to four synchroni zed control signals for left and right eye shutter control. these four lines can o utput pulses with microsecond resolution for on and off timing. t he total cycle time can be set for any period up to 65535 msec. the pulses are synchronized to each other for left and right eye shutters. the cyw20733 seamlessly adjusts the timing of the control signal s based on control messages from the cyw20702, ensuring that the 3d glasses remain synchroni zed to the tv display frame. 3d hardware control on the cyw20733 works independently of th e rest of the system. the cyw 20733 negotiates sniff with the cyw20702 and, except for sniff resynchronization periods, most of the cyw20733 circuitry remains in a low power state while the 3d glasses subsystem continues to provide shutter timi ng and control pul ses. this significantly reduces total system power consumption. 1.17 triac control the cyw20733 includes hardware support for zero-crossing detection and trigger control for up to four triacs. the cyw20733 dete cts zero-crossing on the ac zero detection line and uses that to prov ide a pulse that is offset from the zero crossing. this allows the cyw20733 to be used in dimmer applications, as well as any other applications that require a cont rol signal that is offset from an input event. the zero-crossing hardware includes an option to suppress glitches. see figure . figure 9. triac control (tbd) 1.18 cypress proprietary control signalling and triggered broadcom fast connect cypress proprietary control signaling (bpcs) and triggered br oadcom fast connect (tbfc) are cypress-proprietary baseband (acl) suspension and low-latency reconnection mechanisms that reestablish the baseband connectio n with the peer controller that also supports bpcs/tbfc. the cyw20733 uses bpcs primitives to allow a human interface de vice (hid) to suspend all rf traffic after a configurable idle period with no reportable activity. to conserve power, it can th en enter one of its low power st ates while still logically rema ining connected at the l2cap and hid la yers with the peer device. when an event requires the hid to deliver a report to the peer devi ce, the cyw20733 uses the tbfc and bpcs mec hanisms to reestablish the baseband c onnection and immediately resume l2cap traffic, greatly reducing latency between the event and delivery of the report to the peer device. to achieve power savings and low latencies that cannot be achieved using long sniff in tervals, certain applications may make us e of the cyw20733 broadcom fast connect (bfc) me chanism, which will eliminate the need to ma intain an rf link, while still being abl e to establish acl and l2cap connections much faster than regular methods. 1.19 integrated filterless class-d audio amplifier the cyw20733 has an integrated speaker driver that includes both the digital path and an internal audio amplifier. the digital audio path includes a fifo, lpf, rate adapter, and pwm modulator. th e output of the pwm modulator drives an on-chip class-d high efficiency audio amplifier as shown in the figure below.
document no. 002-14859 rev. *r page 21 of 67 cyw20733 figure 10. class-d block diagram the on-chip class-d audio amplifier is designed to drive up to 200 mw into an 8 ? load and has a range of 20 hz to 20 khz, covering the entire audio spectrum. the amplifier is designed to deliver maximum dynamic range and power efficiency while minimizing quiescent current. the amplifier has two nonoverlapping switch driv ers and a pair of mosfet power switches for bridge-tie load. the digital class-d modulator converts the audio input to a pwm signal that drives the switch driver . the modulator bitstream is re timed by a low-jitter 24/48 mhz clock at the input of the nonoverlappi ng switch drivers, used to prev ent large crowbar currents during switching. a large w/l aspect ratio of the power transistor is used to minimize the on-resistance of the devices for improved e fficiency. the integrated audio amplifier requires a 3.0v regulated po wer supply. the required ldo characteristic is shown in table 11 . 1.20 high-current i/o the cyw20733 has one high-current i/o pin (gpio p57) capable of sinking up to 100 ma with a maximum output voltage of 0.4v (vddio = 3.0v). for vddio = 1.62v, gpio p57 is limited to sinki ng up to 60 ma. this pin can be used for leds, motors, or other high current devices. this pin can also be used as a gpio if high current sink capability is not required. an example usage for driving a motor/vibrator is shown in figure 11 . table 11. ldo requirement for the integrated audio amplifier parameter condition minimum typical maximum unit output voltage ? 2.9 ? 3.1 v output load current ? ? ? 200 ma rms load regulation vin = 2.9v and load current = 200 ma ? ? 40 mv power supply rejection ration (psrr) ? 60 ? ? db output impedance ? ? ? 20 m ? output spot noise at 1 khz ? ? 1.5 ? vrms/ sqrt (hz) output noise ? ? ? 50 ? vrms 16 lpf hi-fi rate adapter pwm modulator ap interface ? - mod. m 16 16 22 from fifo 150 khz 667 khz or 1.33 mhz to class-d audio amplifier 8khz 16 khz 22.05 khz 44.1 khz 48 khz 128 khz 256 khz 352.8 khz 705.6 khz 768 khz 3 m=160or320
document no. 002-14859 rev. *r page 22 of 67 cyw20733 figure 11. motor/vibrator circuit 1.21 power management unit the power management unit (pmu) provides power management features that can be invoked by software through power management registers or packet handling in the baseband core. 1.21.1 rf power management the bbc generates power-down control signals for the transmit path, receive path, pll, and power amplifier to the 2.4 ghz trans - ceiver, which then processes the power-down functions accordingly. 1.21.2 host controller power management power is automatically managed by the firmware based on input dev ice activity. as a power-saving task, the firmware controls th e disabling of the on-chip regulator when in deep-sleep mode. 1.21.3 bbc power management there are several low-power operations for the bbc: physical layer packet handling turns rf on and off dynamically within packet tx and rx. bluetooth-specified low-power connection sn iff mode. while in these low-power connec tion modes, the cyw20733 runs on the low-power oscillator (lpo) and wakes up after a predefined time period. the cyw20733 automatically adjusts its pow er dissipation based on user activity. the following power modes are supported: active mode idle mode suspend mode power-down mode hidoff mode the cyw20733 transitions to the next lower state after a programm able period of user inactivity. busy mode is immediately enter ed when user activity resumes. hidoff mode is one of the power modes in wh ich the core is powered down and only supervi sory circuits running directly from the battery retain power. ma2s111 cyw20733 d1 vcc c1 10 ? uf motor 2 1 12 p57 u1 mg1
document no. 002-14859 rev. *r page 23 of 67 cyw20733 2. pin assignments table 12. pin descriptions pin number pin name i/o power do- main description 81-pin fbga 121-pin fbga 56-pin qfn radio i/o d1 e1 9 rfp i/o vddtf rf antenna port rf power supplies b1 c1 6 vddif i vddif ifpll power supply e1 f1 11 vddlna i vddlna rf front-end supply f1 g1 12 vddrf i vddrf vco, logen supply g1 h1 13 vddpx i vddpx rfpll and crystal oscillator supply c1 d1 7 vddtf i vddtf pa supply power supplies a3, j7 a2, l7 5 vddc i vddc baseband core supply a7 b4, a8, e11 54 vddo i vddo i/o pad and core supply j6 l8 28 vddm i vddm i/o pad supply ? l3 ? vdd1p2 i vdd1p2 speaker differentia l clock conversion power supply ? k10, l10 ? vddsp i vddsp speaker analog power supply ground c2, d2, e2, f2, g2, e3, f3, h3, j3, e4, e5, e6, e7 f8, h7, g7, f7, h6, g6, h5, g5, f5, h4, g4, j3, h3, g3, k2, j2, h2, g2, f2, e2, d2 center paddle vss i vss ground ? k3 ? vss1p2 i ? speaker differential clock conversion ground ? j9, j10, j11 ? vsssp i ? speaker analog ground clock generator and crystal interface j1 k1 16 xtali i vddrf crystal oscillator input. see ?crystal oscillator? on page 10 for options. j2 l1 15 xtalo o vddpx crystal oscillator output. ? c2 ? tp1 i vddpx xtal divide by 2. connect to gnd if main xtal = 24 mhz. h1 j1 14 res o vddpx external calibration resistor, 15 k ? at 1% b4 a3 ? xtali32k i vddpx low-power oscillator (lpo) input. alternate function: ? p39 (fbga-81 only) d5 b3 ? xtalo32k o vddpx lpo output. alternate function: ? p38 (fbga-81 only) core b2 c3 2 reset_n i/o pu vddo active-low sy stem reset with open-drain output and internal pull-up resistor. g3 b2 1 tmc i vddo device test mode control. connect to gnd for all applications. h2 l2 17 tma i vddm arm jtag debug mode control. connect to gnd for all applications. speaker ? l11 ? amplp o vddsp speaker driver positive output ? k11 ? ampln o vddsp speaker driver negative output
document no. 002-14859 rev. *r page 24 of 67 cyw20733 pcm2/i 2 s g5 j8 24 pcm_sync i/o, pd vddm frame synchronization for pcm interface. alternate function: ?i 2 s word select g4 j7 23 pcm_clk i/o, pd vddm clock for pcm interface. alternate function: ?i 2 s clock f4 k7 22 pcm_in i, pu vddm data input for pcm interface. alternate function: ?i 2 s data input f5 k8 25 pcm_out o, pd vddm data output for pcm interface. alternate function: ?i 2 s data output uart j4 k6 20 uart_rxd i vddm uart serial input ? serial data input for the hci uart interface. j5 l6 21 uart_txd o, pu vddm uart serial output ? serial data output for the hci uart interface. h4 l5 19 uart_rts_n o, pu vddm request to send (rts) for hci uart interface. leave unconnected if not used. h5 k5 18 uart_cts_n i, pu vddm clear to send (cts) for hci uart interface. leave unconnected if not used. bsc h6 l9 26 sda i/o, pu vddm data signal for an external i 2 c device. alternate function: ? spi_1: mosi (master only) h7 k9 27 scl i/o, pu vddm clock signal for an external i 2 c device. alternate function: ? spi_1: spi_clk (master only) ldo regulator power supplies a2 a1 3 ldoin i ldoin battery input supply for the ldo a1 b1 4 ldoout o ldoout ldo output table 12. pin descriptions (cont.) pin number pin name i/o power do- main description 81-pin fbga 121-pin fbga 56-pin qfn
document no. 002-14859 rev. *r page 25 of 67 cyw20733 table 13. gpio pin descriptions a pin number pin name default di- rection por state power domain alternate function description 81-pin fbga 121-pin fbga 56-pin qfn h8 h9 29 p0 input floating vddo ? gpio: p0 ? keyboard scan input (row): ksi0 ? a/d converter input 29 ? peripheral uart: puart_tx ? spi_2: mosi (master and slave) ? ir_rx ? 60hz_main note: not available during tmc = 1. j8 g9 31 p1 input floating vddo ? gpio: p1 ? keyboard scan input (row): ksi1 ? a/d converter input 28 ? peripheral uart: puart_rts ? spi_2: miso (master and slave) ?ir_tx j9 h10 30 p2 input floating vddo ? gpio: p2 ? keyboard scan input (row): ksi2 ? quadrature: qdx0 ? peripheral uart: puart_rx ? spi_2: spi_cs (slave only) h9 h11 32 p3 input floating vddo ? gpio: p3 ? keyboard scan input (row): ksi3 ? quadrature: qdx1 ? peripheral uart: puart_cts ? spi_2: spi_clk (master and slave) g8 g10 34 p4 input floating vddo ? gpio: p4 ? keyboard scan input (row): ksi4 ? quadrature: qdy0 ? peripheral uart: puart_rx ? spi_2: mosi (master and slave) ?ir_tx g9 f10 33 p5 input floating vddo ? gpio: p5 ? keyboard scan input (row): ksi5 ? quadrature: qdy1 ? peripheral uart: puart_tx ? spi_2: miso (master and slave) f8 f11 35 p6 input floating vddo ? gpio: p6 ? keyboard scan input (row): ksi6 ? quadrature: qdz0 ? peripheral uart: puart_rts ? spi_2: spi_cs (slave only) ? 60hz_main f9 e10 36 p7 input floating vddo ? gpio: p7 ? keyboard scan input (row): ksi7 ? quadrature: qdz1 ? peripheral uart: puart_cts ? spi_2: spi_clk (master and slave) e8 d11 37 p8 input floating vddo ? gpio: p8 ? keyboard scan output (column): kso0 ? a/d converter input 27 ? external t/r switch control: ~tx_pd
document no. 002-14859 rev. *r page 26 of 67 cyw20733 e9 d10 38 p9 input floating vddo ? gpio: p9 ? keyboard scan output (column): kso1 ? a/d converter input 26 ? external t/r switch control: tx_pd d8 e9 39 p10 input floating vddo ? gpio: p10 ? keyboard scan output (column): kso2 ? a/d converter input 25 ? external pa ramp control: ~pa_ramp d9 c11 41 p11 input floating vddo ? gpio: p11 ? keyboard scan output (column): kso3 ? a/d converter input 24 c9 c10 40 p12 input floating vddo ? gpio: p12 ? keyboard scan output (column): kso4 ? a/d converter input 23 c8 b11 43 p13 input floating vddo ? gpio: p13 ? keyboard scan output (column): kso5 ? a/d converter input 22 ? external pa ramp control: ~pa_ramp ? triac control 3 b9 b10 44 p14 input floating vddo ? gpio: p14 ? keyboard scan output (column): kso6 ? a/d converter input 21 ? external t/r switch control: ~tx_pd ? triac control 4 a9 a11 42 p15 input floating vddo ? gpio: p15 ? keyboard scan output (column): kso7 ? a/d converter input 20 ? ir_rx ? 60hz_main b7 a9 ? p16 input floating vddo ? gpio: p16 ? keyboard scan output (column): kso8 ? a/d converter input 19 b8 a10 ? p17 input floating vddo ? gpio: p17 ? keyboard scan output (column): kso9 ? a/d converter input 18 c7 b9 ? p18 input floating vddo ? gpio: p18 ? keyboard scan output (column): kso10 ? a/d converter input 17 g7 c9 ? p19 input floating vddo ? gpio: p19 ? keyboard scan output (column): kso11 f7 d9 ? p20 input floating vddo ? gpio: p20 ? keyboard scan output (column): kso12 ? a/d converter input 15 d7 e8 ? p21 input floating vddo ? gpio: p21 ? keyboard scan output (column): kso13 ? a/d converter input 14 ? triac control 3 table 13. gpio pin descriptions a (cont.) pin number pin name default di- rection por state power domain alternate function description 81-pin fbga 121-pin fbga 56-pin qfn
document no. 002-14859 rev. *r page 27 of 67 cyw20733 a8 g8 ? p22 input floating vddo ? gpio: p22 ? keyboard scan output (column): kso14 ? a/d converter input 13 ? triac control 4 d6 c6 ? p23 input floating vddo ? gpio: p23 ? keyboard scan output (column): kso15 ? a/d converter input 12 g6 f9 45 p24 input floating vddo ? gpio: p24 ? keyboard scan output (column): kso16 ? spi_2: spi_clk (master and slave) ? spi_1: miso (master only) ? peripheral uart: puart_tx f6 d8 46 p25 input floating vddo ? gpio: p25 ? keyboard scan output (column): kso17 ? spi_2: miso (master and slave) ? peripheral uart: puart_rx a4 a5 56 p26 pwm0 input floating vddo ? gpio: p26 ? keyboard scan output (column): kso18 ? spi_2: spi_cs (slave only) ? spi_1: miso (master only) ? optical control output: qoc0 ? triac control 1 current: 16 ma sink b3 b5 55 p27 pwm1 input floating vddo ? gpio: p27 ? keyboard scan output (column): kso19 ? spi_2: mosi (master and slave) ? optical control output: qoc1 ? triac control 2 current: 16 ma sink c3 a4 ? p28 pwm2 input floating vddo ? gpio: p28 ? optical control output: qoc2 ? a/d converter input 11 ?led1 current: 16 ma sink d3 c4 ? p29 pwm3 input floating vddo ? gpio: p29 ? optical control output: qoc3 ? a/d converter input 10 ?led2 current: 16 ma sink c6 c8 47 p30 input floating vddo ? gpio: p30 ? a/d converter input 9 ? pairing button pin in default fw ? peripheral uart: puart_rts b6 b8 ? p31 input floating vddo ? gpio: p31 ? a/d converter input 8 ? eeprom wp pin in default fw ? peripheral uart: puart_tx table 13. gpio pin descriptions a (cont.) pin number pin name default di- rection por state power domain alternate function description 81-pin fbga 121-pin fbga 56-pin qfn
document no. 002-14859 rev. *r page 28 of 67 cyw20733 a6 b7 48 p32 input floating vddo ? gpio: p32 ? a/d converter input 7 ? quadrature: qdx0 ? spi_2: spi_cs (slave only) ? spi_1: miso (master only) ? auxiliary clock output: aclk0 ? peripheral uart: puart_tx c4 b6 53 p33 input floating vddo ? gpio: p33 ? a/d converter input 6 ? quadrature: qdx1 ? spi_2: mosi (slave only) ? auxiliary clock output: aclk1 ? peripheral uart: puart_rx c5 c7 ? p34 input floating vddo ? gpio: p34 ? a/d converter input 5 ? quadrature: qdy0 ? peripheral uart: puart_rx ? external t/r switch control: tx_pd b5 d7 49 p35 input floating vddo ? gpio: p35 ? a/d converter input 4 ? quadrature: qdy1 ? peripheral uart: puart_cts a5 a7 50 p36 input floating vddo ? gpio: p36 ? a/d converter input 3 ? quadrature: qdz0 ? spi_2: spi_clk (master and slave) ? auxiliary clock output: aclk0 ? battery detect pin in default fw ? external t/r switch control: ~tx_pd d4 a6 ? p37 input floating vddo ? gpio: p37 ? a/d converter input 2 ? quadrature: qdz1 ? spi_2: miso (slave only) ? auxiliary clock output: aclk1 d5 c5 51 p38 input floating vddo ? gpio: p38 ? a/d converter input 1 ? spi_2: mosi (master and slave) ?ir_tx ? xtalo32k (fbga-81 only) b4 d4 52 p39 input floating vddo ? gpio: p39 ? spi_2: spi_cs (slave only) ? spi_1: miso (master only) ? infrared control: ir_rx ? external pa ramp control: pa_ramp ? 60hz_main ? xtali32k (fbga-81 only) ? h8 ? p40 input floating vddo ? gpio: p40 ? pcm2_clk table 13. gpio pin descriptions a (cont.) pin number pin name default di- rection por state power domain alternate function description 81-pin fbga 121-pin fbga 56-pin qfn
document no. 002-14859 rev. *r page 29 of 67 cyw20733 2.1 ball maps this section presents the cyw20733 ball maps. 2.1.1 81-pin fbga ball map figure 12 shows the 81-pin fbga package ball map. ? k4 ? p41 input floating vddo ? gpio: p41 ? pcm2_sync ? f6 ? p42 input floating vddo ? gpio: p42 ? pcm2_di ? j5 ? p43 input floating vddo ? gpio: p43 ? pcm2_do ? j4 ? p44 input floating vddo ? gpio: p44 ? j6 ? p45 input floating vddo ? gpio: p45 ? l4 ? p46 input floating vddo ? gpio: p46 ? e7 ? p47 input floating vddo ? gpio: p47 ? e6 ? p48 input floating vddo ? gpio: p48 ? d6 ? p49 input floating vddo ? gpio: p49 ? e5 ? p50 input floating vddo ? gpio: p50 ? d5 ? p51 input floating vddo ? gpio: p51 ? f4 ? p52 input floating vddo ? gpio: p52 ? f3 ? p53 input floating vddo ? gpio: p53 ? e4 ? p54 input floating vddo ? gpio: p54 ? e3 ? p55 input floating vddo ? gpio: p55 ? d3 ? p56 input floating vddo ? gpio: p56 ? g11 ? p57 input floating vddo ? gpio: p57 ?pwm3 a. during power-on reset, all inputs are disabled. table 13. gpio pin descriptions a (cont.) pin number pin name default di- rection por state power domain alternate function description 81-pin fbga 121-pin fbga 56-pin qfn
document no. 002-14859 rev. *r page 30 of 67 cyw20733 figure 12. 81-pin fbga ball map a g f e d c b h j 7 6 5 4 3 2 1 89 7 6 5 4 3 2 1 89 a g f e d c b h j ldoout vddpx vddrf vddlna rfp vddtf vddif res xtali ldoin vss vss vss vss vss reset_n tma xtalo vddc tmc vss vss p29 pwm3 p28 pwm2 p27 pwm1 vss vss p26 pwm0 pcm_ clk pcm_in vss p37 p33 p39/ xtali32k uart_ rts_n uart_ rxd p32 p24 p25 vss p23 p30 p31 sda vddm p36 pcm_ sync pcm_ out vss p38/ xtalo32k p34 p35 uart_ cts_n uart_ txd vddo p19 p20 vss p21 p18 p16 scl vddc p22 p4 p6 p8 p10 p13 p17 p0 p1 p15 p5 p7 p9 p11 p12 p14 p3 p2
document no. 002-14859 rev. *r page 31 of 67 cyw20733 2.1.2 121-pin fbga ball map figure 13 shows the 121-pin fbga package ball map. figure 13. 121-pin fbga ball map ldoin vddc xtali32k p28 pwm2 p26 pwm0 p37 p36 vddo p16 p17 p15 ldoout tmc xtalo32k vddo p27 pwm1 p33 p32 p31 p18 p14 p13 vddif tp1 reset_n p29 pwm3 p38 p23 p34 p30 p19 p12 p11 vddtf vss p56 p39 p51 p49 p35 p25 p20 p9 p8 rfp vss p55 p54 p50 p48 p47 p21 p10 p7 vddo vddlna vss p53 p52 vss p42 vss vss p24 p5 p6 vddrf vss vss vss vss vss vss p22 p1 p4 p57 vddpx vss vss vss vss vss vss p40 p0 p2 p3 res vss vss p44 p43 p45 pcm_clk pcm_ sync vsssp vsssp vsssp xtali vss vss1p2 p41 uart_ cts_n uart_ rxd pcm_in pcm_out scl vddsp ampln xtalo tma vdd1p2 p46 uart_ rts_n uart_ txd vddc vddm sda vddsp amplp 7 6 5 4 3 2 1 10 11 89 7 6 5 4 3 2 1 10 11 89 a g f e d c b h j k l a g f e d c b h j k l
document no. 002-14859 rev. *r page 32 of 67 cyw20733 2.1.3 56-pin qfn diagram figure 14 shows the 56-pin qfn package. figure 14. 56-pin qfn diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 tmc reset_n ldoin ldoout vddc vddif vddtf nc rfp nc vddlna vddrf vddpx res 15 16 17 18 19 20 21 22 23 24 25 26 27 28 xtalo xtali tma uart_cts_n uart_rts_n uart_rxd uart_txd pcm_in pcm_clk pcm_sync pcm_out sda scl vddm 42 41 40 39 38 37 36 35 34 33 32 31 30 29 p15 p11 p12 p10 p9 p8 p7 p6 p4 p5 p3 p1 p2 p0 56 55 54 53 52 51 50 49 48 47 46 45 44 43 p26 p27 vddo p33 p39 p38 p36 p35 p32 p30 p25 p24 p14 p13
document no. 002-14859 rev. *r page 33 of 67 cyw20733 3. specifications 3.1 electrical characteristics ta b l e 1 4 shows the maximum electrical rating for voltages referenced to the vdd pin. ta b l e 1 5 shows the power supply characteristics for the range t j = 0 to 125c. ta b l e 1 6 shows the digital level characteristics for the ldo (vss = 0v). table 14. maximum electrical rating rating symbol value unit dc supply voltage for rf domain ? 1.32 v dc supply voltage for core domain ? 1.4 v dc supply voltage for vddm domain (uart/i 2 c) ? 3.8 v dc supply voltage for vddo domain ? 3.8 v dc supply voltage for ldoin ? 3.8 v dc supply voltage for vddlna ? 1.4 v dc supply voltage for vddtf ? 3.3 v voltage on input or output pin ? v ss ? 0.3 to v dd + 0.3 v operating ambient temperature range topr 0 to +70 c storage temperature range tstg ?40 to +125 c table 15. power supply parameter minimum a a. overall performance degrades beyond minimum and maximum supply voltages. typical maximum a unit dc supply voltage for rf 1.14 1.2 1.26 v dc supply voltage for core 1.14 1.2 1.26 v dc supply voltage for vddm (uart/i 2 c) 1.62 ? 3.63 v dc supply voltage for vddo 1.62 ? 3.63 v dc supply voltage for ldoin 1.62 ? 3.63 v dc supply voltage for vddlna 1.14 1.2 b b. 1.2v for class 2 output with internal vreg. 1.26 v dc supply voltage for vddtf 1.14 1.2 b 3.3 v table 16. ldo regulator electrical specifications parameter conditions min typ max unit input voltage range ? 1.62 ? 3.63 v default output voltage ? ? 1.2 ? v output voltage range 0.88 ? 1.32 v step size ? 40 80 mv accuracy at any step ?5 ? +5 % load current ? ? ? 60 ma line regulation vin from 1.62 to 3.63v, i load = 30 ma ?0.5 ? 0.5 %v o /v load regulation i load from 1 a to 30 ma, vin = 3.3v, bonding r = 0.3 ? ? 0.1 0.15 %v o /ma quiescent current no load @vin = 3.3v *current limit enabled ?6 a a. includes the bandgap quiescent current. 12 a a power-down current vin = 3.3v, worst@70c ? ? 200 na
document no. 002-14859 rev. *r page 34 of 67 cyw20733 table 17. adc specifications parameter symbol conditions min typ max unit adc characteristics number of input channels ? ? ? 28 ? ? channel switching rate f ch ???187khz input signal range v inp ?0?3.63v reference settling time ? ? 7.5 ? ? ? s input resistance r inp single-ended, input range of 0?1.2v ? 680 ? k ? single-ended, input range of 0?2.4v ? 1.84 ? m ? single-ended, input range of 0?3.6v ? 3 ? m ? input capacitance c inp ???5pf conversion rate f c ? 5.859 ? 187 khz resolution r ? ? 16 ? bits effective number of bits ? in guaranteed performance range ? see table 7 on page 14 ?bits absolute voltage measurement error using on-chip adc firmware driver ? 2 % integral nonlinearity 1 inl in guaranteed performance range ?1 ? 1 lsb 1 differential nonlinearity 1 dnl in guaranteed performance range ?1 ? 1 lsb 1 notes: 1. lsbs are expressed at the 10-bit level. table 18. integrated audio ampl ifier electrical specifications parameter conditions min typ max unit analog supply voltage ? 2.9 3.0 3.1 v digital supply voltage ? 1.08 1.2 1.32 v quiescent current zero digital input ?2?ma power down current ? ? 0.5 ? ? a output power r l = 8 ? 200 240 ? mw maximum efficiency at 200 mw output power ? 70 ? % dynamic range (dr) at ?60 dbfs input 65 68 ? db signal-to-noise plus distortion ratio (sndr) at 200 mw output power ? 40 ? db table 19. digital level a a. this table is also applicable to vddmem domain. characteristics symbol min typ max unit input low voltage v il ??0.4v input high voltage v ih 0.75 vddo ? ? v input low voltage (vddo = 1.62v) v il ??0.4v input high voltage (vddo = 1.62v) v ih 1.2 ??v output low voltage b b. at the specified drive current for the pad. v ol ??0.4v output high voltage b v oh vddo ? 0.4??v input capacitance (vddmem domain) c in ?0.12?pf
document no. 002-14859 rev. *r page 35 of 67 cyw20733 table 20. current consumption, class 1 a a. current consumption measurements are taken at ldoin. ldoin = vddio = 2.6v, vddpa = 3.0v. operational mode conditions typ unit receive (1 mbps) peak current level during reception of a basic-rate packet. 28.2 ma transmit (1 mbps) peak current level during the transmission of a basic-rate packet: gfsk output power = 10 dbm. 63.1 ma receive (edr) peak current level during the reception of a 2 or 3 mbps rate packet. 28.6 ma transmit (edr) peak current level during the trans mission of a 2 or 3 mbps rate packet: edr output power = 8 dbm. 63.7 ma average current dm1/dh1 (rx) average current during basic rate maximum throughput connection, which includes only this packet type. 24.3 ma dm5/dh5 (rx) average current during basic rate maximum throughput connection, which includes only this packet type. 26.3 ma 3dh1 (rx) average current during extended data rate maximum throughput connection which includes only this packet type. 24.9 ma 3dh5 (rx) average current during extended data rate maximum throughput connection, which includes only this packet type. 26.4 ma dm1/dh1 (tx) average current during basic rate maximum throughput connection, which includes only this packet type. 29.6 ma dm5/dh5 (tx) average current during basic rate maximum throughput connection, which includes only this packet type. 47.2 ma 3dh1 (tx) average current during extended data rate maximum throughput connection, which includes only this packet type. 29.7 ma 3dh5 (tx) average current during extended data rate maximum throughput connection, which includes only this packet type. 44.8 ma paging ? 23.7 ma sniff slave (495 ms) based on one attempt and no timeout parameter. quality connection that rarely requires more than minimum packet exchange. sniff master follows the optimal sniff protocol of the cyw20702 master. 290 ? a sniff slave (22.5 ms) ? 2.57 ma sniff slave (11.25 ms) ? 4.93 ma
document no. 002-14859 rev. *r page 36 of 67 cyw20733 table 21. current consumption, class 2 (0 dbm) a a. current consumption measurements are taken at ldoin. ldoin = vddio = 2.6v, vddpa = 1.2v. operational mode conditions typ unit receive (1 mbps) peak current level during the reception of a basic-rate packet. 29.0 ma transmit (1 mbps) peak current level during t he transmission of a basic-rate packet: gfsk output power = 0 dbm. 39.3 ma receive (edr) peak current level during the rec eption of a 2 or 3 mbps rate packet. 30.5 ma transmit (edr) peak current level during the trans mission of a 2 or 3 mbps rate packet: edr output power = 0 dbm. 39.3 ma average current dm1/dh1 (rx) average current during basic rate maximum throughput connection, which includes only this packet type. 22.1 ma dm5/dh5 (rx) average current during basic rate maximum throughput connection, which includes only this packet type. 25.8 ma 3dh1 (rx) average current during extended data rate maximum throughput connection, which includes only this packet type. 22.8 ma 3dh5 (rx) average current during extended data rate maximum throughput connection, which includes only this packet type. 24.7 ma dm1/dh1 (tx) average current during basic rate maximum throughput connection, which includes only this packet type. 22.0 ma dm5/dh5 (tx) average current during basic rate maximum throughput connection, which includes only this packet type. 30.9 ma 3dh1 (tx) average current during extended data rate maximum throughput connection, which includes only this packet type. 22.1 ma 3dh5 (tx) average current during extended data rate maximum throughput connection, which includes only this packet type. 31.6 ma paging ? 22.9 ma sniff slave (495 ms) based on one attempt and no timeout parameter. quality connection that rarely requires more than minimum packet exchange. sniff master follows optimal sniff protocol of cyw20702 master. 240 ? a sniff slave (22.5 ms) ? 2.27 ma sniff slave (11.25 ms) ? 4.46 ma
document no. 002-14859 rev. *r page 37 of 67 cyw20733 3.2 rf specifications table 22. current consumption operational mode conditions typ unit sleep internal lpo is in use. 46.5 ? a hidoff ? 1.1 ? a inquiry scan (1.28 sec.) periodic sc an rate is r1 (1.28 seconds). 540 ? a page scan (r1) periodic scan rate is r1 (1.28 seconds). 490 ? a inquiry scan + page scan (r1) both inquiry and page scans are interlaced together at a periodic scan rate of 1.28 seconds. 940 ? a table 23. receiver rf specifications a,b parameter conditions minimum typical c maximum unit general frequency range ? 2402 ? 2480 mhz rx sensitivity d gfsk, 0.1% ber, 1 mbps ? ?89 ?85 dbm ? /4-dqpsk, 0.01% ber, 2 mbps ? ?91 ?85 dbm 8-dpsk, 0.01% ber, 3 mbps ? ?86 ?81 dbm maximum input gfsk, 1 mbps ? ? ?20 dbm maximum input ? /4-dqpsk, 8-dpsk, 2/3 mbps ? ? ?20 dbm interference performance c/i cochannel gfsk, 0.1% ber ? ? 11 db c/i 1 mhz adjacent channel gfsk, 0.1% ber ? ? 0 db c/i 2 mhz adjacent channel gfsk, 0.1% ber ? ? ?30.0 db c/i > 3 mhz adjacent channel gfsk, 0.1% ber ? ? ?40.0 db c/i image channel gfsk, 0.1% ber ? ? ?9.0 db c/i 1 mhz adjacent to image channel gfsk, 0.1% ber ? ? ?20.0 db c/i cochannel ? /4-dqpsk, 0.1% ber ? ? 13 db c/i 1 mhz adjacent channel ? /4-dqpsk, 0.1% ber ? ? 0 db c/i 2 mhz adjacent channel ? /4-dqpsk, 0.1% ber ? ? ?30.0 db c/i > 3 mhz adjacent channel ? /4-dqpsk, 0.1% ber ? ? ?40.0 db c/i image channel ? /4-dqpsk, 0.1% ber ? ? ?7.0 db c/i 1 mhz adjacent to image channel ? /4-dqpsk, 0.1% ber ? ? ?20.0 db c/i cochannel 8-dpsk, 0.1% ber ? ? 21 db c/i 1 mhz adjacent channel 8-dpsk, 0.1% ber ? ? 5 db c/i 2 mhz adjacent channel 8-dpsk, 0.1% ber ? ? ?25.0 db c/i > 3 mhz adjacent channel 8-dpsk, 0.1% ber ? ? ?33.0 db c/i image channel 8-dpsk, 0.1% ber ? ? 0 db c/i 1 mhz adjacent to image channel 8-dpsk, 0.1% ber ? ? ?13.0 db out-of-band blocking performance (cw) e 30?2000 mhz 0.1% ber ? ?10.0 ? dbm 2000?2399 mhz 0.1% ber ? ?27 ? dbm 2498?3000 mhz 0.1% ber ? ?27 ? dbm 3000 mhz?12.75 ghz 0.1% ber ? ?10.0 ? dbm intermodulation performance f bt, ? f = 5 mhz ? ?39.0 ? ? dbm
document no. 002-14859 rev. *r page 38 of 67 cyw20733 spurious emissions g 30 mhz to 1 ghz ? ? ? ?57 dbm 1 ghz to 12.75 ghz ? ? ? ?47 dbm a. all specifications are single ended. unused inputs are left open. b. all specifications, except typica l, are for commercial temperatures. c. typical operating conditions are 1.22v operating voltage and 25c ambient temperature. d. the receiver sensitivity is measured at a ber of 0.1% on the device interface. e. meets this specification using front-end band-pass filter. f. f0 = ?64 dbm bluetooth-modulated signal, f1 = ?39 dbm sine wave, f2 = ?39 dbm bluetooth-modulated signal, f0 = 2f1 ? f2, and |f2 ? f1| = n 1 mhz, where n is 3, 4, or 5. for the typical case, n = 5. g. includes baseband radiated emissions. table 24. transmitter rf specifications a,b a. all specifications are fo r commercial temperatures. b. all specifications are single-ende d. unused inputs are left open. parameter conditions minimum typical maximum unit general frequency range ? 2402 ? 2480 mhz class1: gfsk tx power cd c. +10 dbm output for gfsk measured with vddtf = 2.9 v. d. power output is measured at the device without a front-end band-pass filter. ?6.510?dbm class1: edr tx power de e. +8 dbm output for edr measured with vddtf = 2.9 v. ?4.58?dbm class 2: gfsk tx power d ??0.53?dbm power control step ? 2 4 6 db modulation accuracy ? /4-dqpsk frequency stability ? ?10 ? 10 khz ? /4-dqpsk rms devm ? ? ? 20 % ? /4-qpsk peak devm ? ? ? 35 % ? /4-dqpsk 99% devm ? ? ? 30 % 8-dpsk frequency stability ? ?10 ? 10 khz 8-dpsk rms devm ? ? ? 13 % 8-dpsk peak devm ? ? ? 25 % 8-dpsk 99% devm ? ? ? 20 % in-band spurious emissions +500 khz ? ? ? ?20 dbc 1.0 mhz < |m ? n| < 1.5 mhz ? ? ? ?26 dbc 1.5 mhz < |m ? n| < 2.5 mhz ? ? ? ?20 dbm |m ? n| > 2.5 mhz ? ? ? ?40 dbm out-of-band spurious emissions 30 mhz to 1 ghz ? ? ? ?36.0 f f. maximum value is the value required for bluetooth qualification. dbm 1 ghz to 12.75 ghz ? ? ? ?30.0 f, g g. meets this specification using a front-end band-pass filter. dbm 1.8 ghz to 1.9 ghz ? ? ? ?47.0 dbm 5.15 ghz to 5.3 ghz ? ? ? ?47.0 dbm table 23. receiver rf specifications a,b (cont.) parameter conditions minimum typical c maximum unit
document no. 002-14859 rev. *r page 39 of 67 cyw20733 3.3 timing and ac characteristics in this section, use the numbers listed in the reference column of each table to interpret the followin g timing diagrams. 3.3.1 uart timing figure 15. uart timing table 25. uart timi ng specifications reference characteristics min max unit 1 delay time, uart_cts_n low to uart_txd valid ? 24 baud out cycles 2 setup time, uart_cts_n high before midpoint of stop bit ? 10 ns 3 delay time, midpoint of stop bit to uart_rts_n high ? 2 baud out cycles 1 2 midpoint ? of ? stop ? bit uart_cts_n uart_txd uart_rxd 3 uart_rts_n
document no. 002-14859 rev. *r page 40 of 67 cyw20733 3.3.2 spi timing figure 16. spi timing diagram table 26. spi1 timing values?sclk = 12 mhz and vddm = 1.8v a a. the sclk period is based on the limitation of tds_mi. sclk is designed for a maximum speed of 12 mhz. the speed can be adjust ed to as low as 400 hz by configuring the firmware. reference characteristics symbol min typical b b. typical timing based on 20 pf//1 m ? load and sclk = 12 mhz. max unit 1 output setup time, from mosi data valid to sample edge of sclk tds_mo ? 23 ? ns 2 output hold time, from sample edge of sclk to mosi data update tdh_mo ? 60 ? ns 3 input setup time, from miso data valid to sample edge of sclk tds_mi ? tbd ? ns 4 input hold time, from sample edge of sclk to miso data update tdh_mi ? tbd ? ns 5 c c. cs timing is firmware controlled. time from cs assert to first sclk edge tsu_cs ? sclk period ? 1 ? ? ns 6 c time from first sclk edge to cs deassert thd_cs ? sclk period ? ? ns mosi 1 2 3 4 sclk mode ? 1 miso cs 5 invalid ? bit msb msb lsb lsb 6 sclk mode ? 3
document no. 002-14859 rev. *r page 41 of 67 cyw20733 3.3.3 bsc interface timing the specifications in table 29 and table 30 on page 43 reference figure 17 on page 43 . table 27. spi1 timing values?sclk = 12 mhz and vddm = 3.3v a a. the sclk period is based on the limitation of tds_mi. sclk is designed for a maximum speed of 12 mhz. the speed can be adjust ed to as low as 400 hz by configuring the firmware. reference characteristics symbol min typical b b. typical timing based on 20 pf//1 m ? load and sclk = 12 mhz. max unit 1 output setup time, from mosi data valid to sample edge of sclk tds_mo ? 34 ? ns 2 output hold time, from sample edge of sclk to mosi data update tdh_mo ? 49 ? ns 3 input setup time, from miso data valid to sample edge of sclk tds_mi ? tbd ? ns 4 input hold time, from sample edge of sclk to miso data update tdh_mi ? tbd ? ns 5 c c. cs timing is firmware controlled. time from cs assert to first sclk edge tsu_cs ? sclk period ? 1 ? ? ns 6 c time from first sclk edge to cs deassert thd_cs ? sclk period ? ? ns table 28. spi2 timing values?sclk = 6 mhz and vddm = 3.3v a a. the sclk period is based on the limitation of tds_mi. sclk is designed for a maximum speed of 6 mhz. the speed can be adjuste d to as low as 400 hz by configuring the firmware. reference characteristics symbol min typical b b. typical timing based on 20 pf//1 m ? load and sclk = 6 mhz. max unit 1 output setup time, from mosi data valid to sample edge of sclk tds_mo ? 67 ? ns 2 output hold time, from sample edge of sclk to mosi data update tdh_mo ? 99 ? ns 3 input setup time, from miso data valid to sample edge of sclk tds_mi ? tbd ? ns 4 input hold time, from sample edge of sclk to miso data update tdh_mi ? tbd ? ns 5 c c. cs timing is firmware controlled in master mode and can be adjusted as required in slave mode. time from cs assert to first sclk edge tsu_cs ? sclk period ? 1 ? ? ns 6 c time from first sclk edge to cs deassert thd_cs ? sclk period ? ? ns table 29. bsc interface timing specifications (up to 1 mhz) reference characteristics min max unit 1 clock frequency ? 100 khz 400 800 1000 2 start condition setup time 650 ? ns 3 start condition hold time 280 ? ns 4 clock low time 650 ? ns 5 clock high time 280 ? ns 6 data input hold time a 0 ? ns 7 data input setup time 100 ? ns
document no. 002-14859 rev. *r page 42 of 67 cyw20733 8 stop condition setup time 280 ? ns 9 output valid from clock ? 400 ns 10 bus free time b 650 ? ns a. as a transmitter, 125 ns of delay is provided to bridge t he undefined region of the falling edge of scl to avoid unintended g eneration of start or stop conditions. b. time that the cbus must be free before a new transaction can start. table 29. bsc interface timing specifications (up to 1 mhz) reference characteristics min max unit
document no. 002-14859 rev. *r page 43 of 67 cyw20733 figure 17. bsc interface timing diagram 3.3.4 pcm interface timing the following is a list of the pcm interface timing diagrams. pcm electrical timing slave ? short frame sync pcm electrical timing master?short frame sync pcm electrical timing burst (slave rx only)?short frame sync table 30. bsc interface timing specification (1 mhz through 4 mhz) reference characteristics min max unit 1 clock frequency a a. maximum speed is achieved without clock stretching. st rict timing parameter adherence for modes beyond i 2 c fast mode may require that the total capacitance of the sda and scl traces be very similar so that signal transition times are very similar. 1.000 4.000 mhz 2 start condition setup time 233 ? ns 3 start condition hold time 66 ? ns 4 clock low time b b. programmable by firmware. use 50% of period for overclocking frequencies greater than 2.400 mhz. can be asymmetric (65/35 duty ) for modest overclocking?up to 2.400 mhz. ? scl period ? ns 5 clock high time b ? scl period ? ns 6 data input hold time c c. as a transmitter, 125 ns of delay is provided to bridge the undefined region of the falling edge of scl to avoid unintended ge neration of start or stop conditions. 0? ns 7 data input setup time d d. depends on the degree of overclocking. application-specific programmability of the hardware block can affect this parameter. 33.4 ? ns 8 stop condition setup time 233 ? ns 9 output valid from clock ? 150 ns 10 bus free time e e. time that cbus must be free before a new transaction can start. 650 ? ns 2 8 scl sda in sda out 7 6 1 5 10 3 4 9
document no. 002-14859 rev. *r page 44 of 67 cyw20733 pcm electrical timing slave?long frame sync pcm electrical timing master?long frame sync pcm electrical timing burst (slave rx only)?long frame sync note: the tx and rx timings are combined on the same diagram. the cy w20733 can only either transmit or receive in a given slot. pcm electrical timing slave ? short frame sync figure 18. pcm electrical timing slave?short frame sync diagram table 31. pcm electrical timing slave ?short frame sync characteristics reference characteristics minimum typical maximum unit 1 pcm bit clock frequency ? ? 12 mhz 2 pcm bit clock low time 41 ? ? ns 3 pcm bit clock high time 41 ? ? ns 4 pcm_sync setup time 8 ? ? ns 5 pcm_sync hold time 8 ? ? ns 6 pcm_out delay 0 ? 25 ns 7 pcm_in setup 8 ? ? ns 8 pcm_in hold 8 ? ? ns 9 delay from rising edge of pcm_bclk during last bit period to pcm_out becoming high impedance 0 ? 25 ns pcm_bclk pcm_sync pcm_out 1 2 3 4 5 6 pcm_in 7 9 high ? impedance 8 bit ? 15 ? (previous ? frame) bit ? 15 ? (previous ? frame) bit ? 0 bit ? 0
document no. 002-14859 rev. *r page 45 of 67 cyw20733 pcm electrical timing master?short frame sync figure 19. pcm electrical timing master?short frame sync diagram pcm electrical timing burst (s lave rx only)?short frame sync figure 20. pcm electrical ti ming burst (slave rx-only)?short frame sync diagram table 32. values of pcm electrical timing master?short frame sync characteristics reference characteristics minimum typical maximum unit 1 pcm bit clock frequency ? ? 12 mhz 2 pcm bit clock low time 41 ? ? ns 3 pcm bit clock high time 41 ? ? ns 4 pcm_sync delay 0 ? 25 ns 5 pcm_out delay 0 ? 25 ns 6 pcm_in setup 8 ? ? ns 7 pcm_in hold 8 ? ? ns 8 delay from rising edge of pcm_bclk during last bit period to pcm_out becoming high impedance 0 ? 25 ns pcm_bclk pcm_sync pcm_out 1 2 3 4 5 pcm_in 6 8 high ? impedance 7 bit ? 15 ? (previous ? frame) bit ? 15 ? (previous ? frame) bit ? 0 bit ? 0 pcm_bclk pcm_sync 1 2 3 4 5 pcm_in 6 7 bit ? 15 ? (previous ? frame) bit ? 0
document no. 002-14859 rev. *r page 46 of 67 cyw20733 pcm electrical timing slave?long frame sync figure 21. pcm electrical timing slave?long frame sync diagram table 33. values of pcm electrical timing burst (slave rx-only)?short frame sync characteristics reference characteristics minimum typical maximum unit 1 pcm bit clock frequency ? ? 24 mhz 2 pcm bit clock low time 20.8 ? ? ns 3 pcm bit clock high time 20.8 ? ? ns 4 pcm_sync setup time 8 ? ? ns 5 pcm_sync hold time 8 ? ? ns 6 pcm_in setup 8 ? ? ns 7 pcm_in hold 8 ? ? ns table 34. values of pcm electrical timi ng slave?long frame sync characteristics reference characteristics minimum typical maximum unit 1 pcm bit clock frequency ? ? 12 mhz 2 pcm bit clock low time 41 ? ? ns 3 pcm bit clock high time 41 ? ? ns 4 pcm_sync setup time 8 ? ? ns 5 pcm_sync hold time 8 ? ? ns 6 pcm_out delay 0 ? 25 ns 7 pcm_in setup 8 ? ? ns 8 pcm_in hold 8 ? ? ns 9 delay from rising edge of pcm_bclk during last bit period to pcm_out becoming high impedance 0 ? 25 ns pcm_bclk pcm_sync pcm_out 1 2 3 4 5 6 pcm_in 7 9 high ? impedance 8 bit ? 0 bit ? 0 bit ? 1 bit ? 1
document no. 002-14859 rev. *r page 47 of 67 cyw20733 pcm electrical timing master?long frame sync figure 22. pcm electrical timing master?long frame sync diagram pcm electrical timing burst (slave rx only)?long frame sync figure 23. pcm electrical timing burst (slave rx-only)?long frame sync diagram table 35. values of pcm electrical timing master?long frame sync characteristics reference characteristics minimum typical maximum unit 1 pcm bit clock frequency ? ? 12 mhz 2 pcm bit clock low time 41 ? ? ns 3 pcm bit clock high time 41 ? ? ns 4 pcm_sync delay 0 ? 25 ns 5 pcm_out delay 0 ? 25 ns 6 pcm_in setup 8 ? ? ns 7 pcm_in hold 8 ? ? ns 8 delay from rising edge of pcm_bclk during last bit period to pcm_out becoming high impedance 0 ? 25 ns pcm_bclk pcm_sync pcm_out 1 2 3 4 5 pcm_in 6 8 high ? impedance 7 bit ? 0 bit ? 0 bit ? 1 bit ? 1 pcm_bclk pcm_sync 1 2 3 4 5 pcm_in 6 7 bit ? 0 bit ? 1
document no. 002-14859 rev. *r page 48 of 67 cyw20733 3.3.5 i 2 s timing the following is a list of the i 2 s timing diagrams. i 2 s electrical timing slave?short frame ws i 2 s electrical timing master?short frame ws i 2 s electrical timing burst (slave rx only)?short frame ws i 2 s electrical timing slave?long frame ws i 2 s electrical timing master?long frame ws i 2 s electrical timing burst (slave rx only)?long frame ws note: the tx and rx timings are combined on the same diagram. the cy w20733 can only either transmit or receive in a given slot. i 2 s electrical timing slave?short frame ws figure 24. i 2 s electrical timing slave ? short frame ws diagram table 36. values of pcm electrical timing burst (slave rx only)?long frame sync characteristics reference characteristics minimum typical maximum unit 1 pcm bit clock frequency ? ? 24 mhz 2 pcm bit clock low time 20.8 ? ? ns 3 pcm bit clock high time 20.8 ? ? ns 4 pcm_sync setup time 8 ? ? ns 5 pcm_sync hold time 8 ? ? ns 6 pcm_in setup 8 ? ? ns 7 pcm_in hold 8 ? ? ns table 37. values of i 2 s electrical timing slave?short frame ws characteristics reference characteristics minimum typical maximum unit 1i 2 s bit clock frequency ? ? 12 mhz 2i 2 s bit clock low time 41 ? ? ns 3i 2 s bit clock high time 41 ? ? ns 4 i2s_ws setup time 8 ? ? ns 5 i2s_out delay 0 ? 25 ns i2s_bclk i2s_ws i2s_out 1 2 3 4 5 i2s_in 6 7 bit ? 15 ? (previous ? frame) bit ? 15 ? (previous ? frame) bit ? 0 bit ? 0
document no. 002-14859 rev. *r page 49 of 67 cyw20733 i 2 s electrical timing master?short frame ws figure 25. i 2 s electrical timing master ? short frame ws diagram 6 i2s_in setup 8 ? ? ns 7 i2s_in hold 8 ? ? ns table 38. values of i 2 s electrical timing master?sho rt frame ws characteristics reference characteristics minimum typical maximum unit 1i 2 s bit clock frequency ? ? 12 mhz 2i 2 s bit clock low time 41 ? ? ns 3i 2 s bit clock high time 41 ? ? ns 4 i2s_ws delay 0 ? 25 ns 5 i2s_out delay 0 ? 25 ns 6 i2s_in setup 8 ? ? ns 7 i2s_in hold 8 ? ? ns table 37. values of i 2 s electrical timing slave?short frame ws characteristics reference characteristics minimum typical maximum unit i2s_bclk i2s_ws i2s_out 1 2 3 4 5 i2s_in 6 7 bit ? 15 ? (previous ? frame) bit ? 15 ? (previous ? frame) bit ? 0 bit ? 0
document no. 002-14859 rev. *r page 50 of 67 cyw20733 i 2 s electrical timing burst (slave rx only)?short frame ws figure 26. i 2 s electrical timing burst (slave rx only) ? short frame ws diagram i 2 s electrical timing slave?long frame ws figure 27. i 2 s electrical timing slave ? long frame ws diagram table 39. values of i 2 s electrical timing burst (slave rx-o nly)?short frame ws characteristics reference characteristics minimum typical maximum unit 1i 2 s bit clock frequency ? ? 24 mhz 2 i2s bit clock low time 20.8 ? ? ns 3i 2 s bit clock high time 20.8 ? ? ns 4 i2s_ws setup time 8 ? ? ns 5 i2s_in setup 8 ? ? ns 6 i2s_in hold 8 ? ? ns i2s_bclk i2s_ws 1 2 3 4 i2s_in 5 6 bit ? 15 ? (previous ? frame) bit ? 0 i2s_bclk i2s_ws i2s_out 1 2 3 4 5 i2s_in 6 7 bit ? 0 bit ? 0 bit ? 1 bit ? 1
document no. 002-14859 rev. *r page 51 of 67 cyw20733 i 2 s electrical timing master?long frame ws figure 28. i 2 s electrical timing master ? long frame ws diagram table 40. values of i 2 s electrical timing slave?long frame ws characteristics reference characteristics minimum typical maximum unit 1i 2 s bit clock frequency ? ? 12 mhz 2i 2 s bit clock low time 41 ? ? ns 3i 2 s bit clock high time 41 ? ? ns 4 i2s_ws setup time 8 ? ? ns 5 i2s_out delay 0 ? 25 ns 6 i2s_in setup 8 ? ? ns 7 i2s_in hold 8 ? ? ns table 41. values of i 2 s electrical timing master?l ong frame ws characteristics reference characteristics minimum typical maximum unit 1i 2 s bit clock frequency ? ? 12 mhz 2i 2 s bit clock low time 41 ? ? ns 3i 2 s bit clock high time 41 ? ? ns 4 i2s_ws delay 0 ? 25 ns 5 i2s_out delay 0 ? 25 ns 6 i2s_in setup 8 ? ? ns 7 i2s_in hold 8 ? ? ns i2s_bclk i2s_ws i2s_out 1 2 3 4 5 i2s_in 6 7 bit ? 0 bit ? 0 bit ? 1 bit ? 1
document no. 002-14859 rev. *r page 52 of 67 cyw20733 i 2 s electrical timing burst (slave rx only)?long frame ws figure 29. i 2 s electrical timing burst (slave rx only) ? long frame ws diagram table 42. values of i 2 s electrical timing burst (slave rx only)?long frame ws characteristics reference characteristics minimum typical maximum unit 1i 2 s bit clock frequency ? ? 24 mhz 2i 2 s bit clock low time 20.8 ? ? ns 3i 2 s bit clock high time 20.8 ? ? ns 4 i2s_ws setup time 8 ? ? ns 5 i2s_in setup 8 ? ? ns 6 i2s_in hold 8 ? ? ns i2s_bclk i2s_ws 1 2 3 4 i2s_in 5 6 bit ? 0 bit ? 1
document no. 002-14859 rev. *r page 53 of 67 cyw20733 4. mechanical information figure 30. 81-pin fbga
document no. 002-14859 rev. *r page 54 of 67 cyw20733 figure 31. 121-pin fbga
document no. 002-14859 rev. *r page 55 of 67 cyw20733 figure 32. 56-pin qfn
document no. 002-14859 rev. *r page 56 of 67 cyw20733 4.0.1 tape reel and packaging specifications table 43. cyw20733 8 8 1.0 mm fb ga 81-pin tape reel specifications quantity per reel 2500 pieces reel diameter 13 inches hub diameter 7 inches tape width 16 mm tape pitch 12 mm table 44. cyw20733 9 x 9 x 1.0 mm fbga 121-pin tape reel specifications quantity per reel 1500 pieces reel diameter 13 inches hub diameter 4 inches tape width 16 mm tape pitch 12 mm table 45. cyw20733 7 x 7 x 1.0 mm qfn 56-pin tape reel specifications quantity per reel 2500 pieces reel diameter 13 inches hub diameter 7 inches tape width 16 mm tape pitch 12 mm
document no. 002-14859 rev. *r page 57 of 67 cyw20733 figure 33. cyw20733 reel/label ing/packaging specification reel specifications: device orientation/mix lot number: (dfk5hhopd\frqwdlqxswrwkuhh lqglylgxdoorwqxpehuvzlwklq zrunzhhnv 7khvhlqglylgxdoorwvpxvweh odehohgrqwkher[prlvwxuheduu lhuedjdqguhho 3lq7rs/hiw&ruqhu7rsrisdfn djhwrzdug6surfnhw+rohv & &\suhvv%dufrgh/deho (per standard barcode label specification ? p-pde-1101) (6':duqlqj 0rlvwxuh6hqvlwlylw\6wlfnhu (per msl labeling specification ? p-pde-1051)
document no. 002-14859 rev. *r page 58 of 67 cyw20733 figure 34. cyw20733 9 9 fbga package tray (1 of 2)
document no. 002-14859 rev. *r page 59 of 67 cyw20733 figure 35. cyw20733 9 9 fbga package tray (2 of 2)
document no. 002-14859 rev. *r page 60 of 67 cyw20733 figure 36. cyw20733 8 8 fbga package tray (1 of 2)
document no. 002-14859 rev. *r page 61 of 67 cyw20733 figure 37. cyw20733 8 8 fbga package tray (2 of 2) notes: 1. tray shall conform to jedec cs-004 standard on thin matrix trays for mqfp package. 2. tray surfaces to be free of seams. 3. iqa specification sac-x042 shall apply. 4. material: mppo, 150 degree c (max), black, stock num 215-4004-508, 12x29 matrix
document no. 002-14859 rev. *r page 62 of 67 cyw20733 5. ordering information 6. iot resources cypress provides a wealth of data at http://www.cypress.com /internet-things-iot to help you to select th e right iot device for your design, and quickly and effectively integrate the device into your design. cypress provides customer access to a wide range of information, including technical documentat ion, schematic diagrams, product bill of ma terials, pcb layout information, and soft ware updates. customers can acquire technica l documentation and soft ware from the cypress support community website (http:// community.cypress.com/). a. acronyms and abbreviations the following list of acronyms and abbrev iations may appear in this document. for a more complete list of acronyms and other terms used in cypress documents, go to: http://www.cypre ss.com/glossary table 46. ordering information part number package ambient operating temperature cyw20733a3kfb1g commercial 81-pin fbga 0c to 70c cyw20733a3kfb2g commercial 121-pin fbga 0c to 70c cyw20733a3kml1g commercial 56-pin qfn 0c to 70c acronym description adc analog-to-digital converter afh adaptive frequency hopping ahb advanced high-performance bus apb advanced peripheral bus apu audio processing unit arm7tdmi-s? acorn risc machine 7 thumb instruction, debugger, multiplier, ice, synthesizable bsc broadcom serial control btc bluetooth? controller coex coexistence dfu device firmware update dma direct memory access ebi external bus interface hci host control interface hv high voltage idc initial digital calibration if intermediate frequency irq interrupt request jtag joint test action group lcu link control unit ldo low drop-out lhl lean high land lpo low power oscillator lv logicvision? mia multiple interface agent pcm pulse code modulation pll phase locked loop pmu power management unit
document no. 002-14859 rev. *r page 63 of 67 cyw20733 por power-on reset pwm pulse width modulation qd quadrature decoder ram random access memory rf radio frequency rom read-only memory rx/tx receive, transmit spi serial peripheral interface sw software uart universal asynchronous receiver/transmitter upi -processor interface usb universal serial bus wd watchdog acronym description
document no. 002-14859 rev. *r page 64 of 67 cyw20733 document history document title: cyw20733 single-chip bluetooth transceiver wireless input devices document number: 002-14859 revision ecn orig. of change submission date description of change ** ? ? 07/23/2010 20733-ds00-r initial release *a ? ? 07/20/2010 updated: table 10: ?pin descriptions,? on page 35 and table 11: ?gpio pin descriptions,? on page 38. figure 13: ?81-pin fbga ball map,? on page 44. table 16: ?integrated audio amplifier el ectrical specifications,? on page 48. table 25: ?pcm electrical timing slave? short frame sync characteristics,? on page 57. table 26: ?values of pcm electrical ti ming master?short frame sync character- istics,? on page 58. ?pcm interface timing? on page 57. ?i2s timing? on page 63. *b ? ? 08/30/2010 20733-ds02-r updated: ?microprocessor unit? on page 13: rom memory capacity. ?link control layer? on page 15: bluetooth link controller tasks. ?uart interface? on page 17: normal baud rate mode. ?gpio port? on page 23. ?theory of operation? on page 25: mouse decoder pwms. ?adc port? on page 26: analog input channels. table 7: ?cyw20733 first spi set (master mode),? on page 28. table 11: ?pin descriptions,? on page 35 and table 12: ?gpio pin descriptions,? on page 37. figure 13: ?81-pin fbga ball map,? on page 44. added: ?peripheral uart interface? on page 19. *c ? ? 10/25/2010 20733-ds03-r updated: ?general description? and ?features? on page 1 tbd for second package changed to 121-pin, 9 mm x 9 mm fbga, throughout the document. table 11: ?pin descriptions,? on page 39 (added 121-pin info) table 12: ?gpio pin descriptions,? on page 41 (added 121-pin info) figure 14: ?121-pin fbga ball map,? on page 49 (added) figure 30: ?81-pin fbga,? on page 73 figure 31: ?121-pin fbga,? on page 74 (121-pin outline drawing, added) table 38: ?cyw20733 8 8 1.0 mm fbga tbd tape reel specifications,? on page 75 table 39: ?cyw20733m 9 x 9 x 1.0 mm fbga tbd tape reel specifications,? on page 75 figure 33: ?cyw20733 99 fbga package tray (1 of 2),? on page 77 figure 35: ?cyw20733 88 fbga package tray (1 of 2),? on page 79 table 40: ?ordering information,? on page 81 *d ? ? 04/04/2011 20733-ds04-r updated: figure 1: ?functional block diagram,? on page 2 ?uart interface? on page 19 table 1: ?common baud rate examples,? on page 20 table 5: ?xtal oscillator characteristics,? on page 25 ?port 0?port 1, port 8 ? port 18, port 20 ? port 23, and port 28 ? port 38? on page 26 table 6: ?sampling rate and effective number of bits,? on page 29 table 12: ?gpio pin descriptions,? on page 40 table 16: ?adc specifications,? on page 50 table 19: ?current consumption, class 1,? on page 52 table 20: ?current consumption, class 2 (0 dbm),? on page 53 (added) table 21: ?receiver rf specifications? on page 54 table 22: ?transmitter rf specifications,? on page 55 section 5: ?ordering information,? on page 81
document no. 002-14859 rev. *r page 65 of 67 cyw20733 *e ? ? 06/29/2011 20733-ds05-r updated: figure 1: ?functional block diagram,? on page 2 ?gpio port? on page 25 ?high current i/o? on page 34 table 10: ?pin descriptions,? on page 36 figure 13: ?121-pin fbga ball map,? on page 46 table 15: ?adc specifications,? on page 48 table 17: ?current consumption, class 1,? on page 49 table 18: ?current consumption, class 2 (0 dbm),? on page 51 added: table 19: ?current consumption,? on page 52removed: ?integrated filterless class-d audio amplifier,? on page 35 table 16: ?integrated audio amplifier el ectrical specifications,? on p. 49. *f ? ? 03/01/2012 20733-ds06-r updated: table 7: ?cyw20733 first spi set (master mode),? on page 32 table 10: ?pin descriptions,? on page 38 table 11: ?gpio pin descriptions,? on page 41 table 15: ?adc specifications,? on page 52 table 17: ?current consumption, class 1,? on page 53 table 18: ?current consumption, class 2 (0 dbm),? on page 55 notes in table 20 on page 57 and table 21 on page 59 table 23: ?values of spi1 timing characteristics,? on page 61 table 39: ?cyw20733 8 8 1.0 mm fbga 81-pin tape reel specifications,? on page 80 table 40: ?cyw20733 9 x 9 x 1.0 mm fbga 121-pin tape reel specifications,? on page 80 added: information related to the 56-pin qfn package on page 1 ?56-pin qfn diagram? on page 50 table 24: ?values of spi2 timing characteristics,? on page 62 figure 32: ?56-pin qfn,? on page 79 table 41: ?cyw20733 7 x 7 x 1.0 mm qfn 56-pin tape reel specifications,? on page 80 figure 33: ?cyw20733 reel/labeling/pa ckaging specification,? on page 81 *g ? ? 03/19/2012 20733-ds07-r updated: notes in table 23: ?values of spi1 timing characteristics,? on page 65 and table 24: ?values of spi2 timing characteristics,? on page 66 *h ? ? 05/18/2012 20733-ds08-r updated: table 8: ?cyw20733 second spi set (master mode),? on page 33. table 9: ?cyw20733 second spi set (slave mode),? on page 34. *i ? ? 06/08/2012 20733-ds09-r updated: bluetooth hid profile version 1.0 to 1.1 on the cover page. ?calibration? on page 15. ?triac control? on page 38. ?cypress proprietary cont rol signalling and triggered br oadcom fast connect? on page 38. table 15: ?adc specifications,? on page 56 by fixing the conditions for the reference settling time and input resistance parameters. table 20: ?receiver rf specifications? on page 59 by updating df to uf in the inter- modulation performance row. ?spi timing? on page 63. *j ? ? 08/30/2012 20733-ds10-r updated: table 43: ?ordering information,? on page 89. *k ? ? 10/01/2012 20733-ds11-r updated: cover page features to incl ude class-d audio amplifier. figure 1: ?functional block diagram,? on page 2 by adding class-d audio driver. table 11: ?pin descriptions,? on page 43. figure 14: ?56-pin qfn diagram,? on page 55. added: ?integrated filterless class-d audio amplifier? on page 40. table 17: ?integrated audio amplifier el ectrical specifications,? on page 58 document title: cyw20733 single-chip bluetooth transceiver wireless input devices document number: 002-14859
document no. 002-14859 rev. *r page 66 of 67 cyw20733 *l ? ? 11/26/2012 20733-ds12-r updated: table 17: ?integrated audio amplifier el ectrical specifications,? on page 58. table 21: ?current consumption,? on page 61. *m ? ? 01/21/2013 20733-ds13-r updated: table 12: ?gpio pin descriptions,? on page 46. *n ? ? 05/31/2013 20733-ds14-r updated: table 45: ?ordering information,? on page 91. *o ? ? 08/12/2013 20733-ds15-r updated: table 21: ?current consumption,? on page 62. *p ? ? 09/25/2013 20733-ds16-r updated: table 4: ?reference crystal electr ical specifications,? on page 26. *q ? ? 07/10/2015 20733-ds17-r updated document status. *r 5487130 utsv 10/21/2016 updated to cypress template added cypress part numbering scheme document title: cyw20733 single-chip bluetooth transceiver wireless input devices document number: 002-14859
document no. 002-14859 rev. *r revised october 21, 2016 page 67 of 67 cyw20733 ? cypress semiconductor corporation, 2010-2016. this document is the property of cypress semiconductor corporation and its subs idiaries, including spansion llc (?cypress?). this document, including any software or firmware included or referenced in this document (?software?), is owned by cypress under the intellec tual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragra ph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a written agreement with cypress governing the use of the software, then cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the software (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hard ware products, only internally within your organization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cypress hardware product units, and (2) u nder those claims of cypress's patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely for use with cypress hardware product s. any other use, reproduction, modi fication, translation, or compilation of the software is prohibited. to the extent permitted by applicable law, cypress makes no warranty of any kind, express or implied, with regard to this docum ent or any software or accompanying hardware, including, but not limited to, the im plied warranties of merchantability and fitness for a particular purpose. to the extent permitted by applicable law, cypress reserves the right to make changes to this document without further notice. cypress does n ot assume any liability arising out of the application or use of any product or circuit described in this document. any information pr ovided in this document, includ ing any sample design informati on or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any appli cation made of this information and any resulting product. cypress products are not designed, intended, or authorized fo r use as critical components in systems de signed or intended for the operation of w eapons, weapons systems, nuclear in stallations, life-support devices or systems, other medical devices or systems (inc luding resuscitation equipment and surgical implants), pollution control or hazar dous substances management, or other uses where the failure of the device or system could cause personal injury , death, or property damage (?unintended uses?). a critical component is any compon ent of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affe ct its safety or effectiveness. cypress is not liable, in whol e or in part, and you shall and hereby do release cypress from any claim, damage, or other liability arising from or related to all unintended uses of cypress products. you shall indemnify and hold cyp ress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal inju ry or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, wiced, psoc, capsense, ez-usb, f-ram, and tra veo are trademarks or registered trademarks of cypress in the united states and other countries. for a more complete list of cypress trademarks, visit cypress.com. other names and brand s may be claimed as property of their respective owners. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution cent ers, manufacturer?s representativ es, and distributors. to find t he office closest to you, visit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/arm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/interface internet of things cypress.com/iot lighting & power control cypress.com/powerpsoc memory cypress.com/memory psoc cypress.com/psoc touch sensing cypress.com/touch usb controllers cypress.com/usb wireless/rf cypress.com/wireless psoc ? solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community forums | wiced iot forums | projects | video | blogs | training | components technical support cypress.com/support 67

▲Up To Search▲

Price & Availability of BCM20733

	To Download BCM20733 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .